+-- `Deep Thought', a softcore CPU implemented on a FPGA
+--
+-- Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+-- Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+-- Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+-- Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+-- Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
port(
--System input pins
sys_res : in std_logic;
- sys_clk : in std_logic;
+ soft_res : in std_logic;
+ sys_clk_in : in std_logic;
-- result : out gp_register_t;
-- reg_wr_data : out gp_register_t
-- uart
bus_tx : out std_logic;
bus_rx : in std_logic;
- led2 : out std_logic;
+ led2 : out std_logic
- sseg0 : out std_logic_vector(0 to 6);
- sseg1 : out std_logic_vector(0 to 6);
- sseg2 : out std_logic_vector(0 to 6);
- sseg3 : out std_logic_vector(0 to 6)
+ --sseg0 : out std_logic_vector(0 to 6);
+ --sseg1 : out std_logic_vector(0 to 6);
+ --sseg2 : out std_logic_vector(0 to 6);
+ --sseg3 : out std_logic_vector(0 to 6)
);
end core_top;
constant SYNC_STAGES : integer := 2;
constant RESET_VALUE : std_logic := '0';
+ signal sys_clk : std_logic;
+
signal jump_result : instruction_addr_t;
signal jump_result_pin : instruction_addr_t;
signal prediction_result_pin : instruction_addr_t;
signal gpm_out_pin : gp_register_t;
signal nop_pin : std_logic;
- signal sync : std_logic_vector(1 to SYNC_STAGES);
- signal sys_res_n : std_logic;
+ signal sync, sync2 : std_logic_vector(1 to SYNC_STAGES);
+ signal sys_res_n, soft_res_n : std_logic;
signal int_req : interrupt_t;
signal im_addr, im_data : gp_register_t;
signal vers, vers_nxt : exec2wb_rec;
+
+
+ component pll
+ PORT
+ (
+ inclk0 : IN STD_LOGIC := '0';
+ c0 : OUT STD_LOGIC
+ );
+ end component;
begin
+ pll_inst : pll PORT MAP (
+ inclk0 => sys_clk_in,
+ c0 => sys_clk
+ );
+
+
fetch_st : fetch_stage
generic map (
--System inputs
clk => sys_clk, --: in std_logic;
reset => sys_res_n, --: in std_logic;
- s_reset => '1',
+ s_reset => soft_res_n,
--Data inputs
jump_result => jump_result_pin, --: in instruction_addr_t;
prediction_result => prediction_result_pin, --: in instruction_addr_t;
port map (
--System inputs
clk => sys_clk, --: in std_logic;
- reset => sys_res_n, -- : in std_logic;
+ reset => sys_res_n and soft_res_n, -- : in std_logic;
--Data inputs
instruction => instruction_pin, --: in instruction_word_t;
exec_st : execute_stage
generic map('0')
- port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+ port map(sys_clk, sys_res_n and soft_res_n, to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
--
writeback_st : writeback_stage
- generic map('0', '1', "altera")
- port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
+ generic map('0', '1', "altera", 5208)
+ port map(sys_clk, sys_res_n and soft_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
-- instruction memory program port :D
new_im_data, im_addr, im_data,
- sseg0, sseg1, sseg2, sseg3, int_req);
+ --sseg0, sseg1, sseg2, sseg3,
+ int_req);
-syn: process(sys_clk, sys_res)
+syn: process(sys_clk, sys_res, soft_res)
begin
-- vers.byte_s <= '0';
sync <= (others => '0');
+ sync2 <= (others => '0');
elsif rising_edge(sys_clk) then
-- vers <= vers_nxt;
for i in 2 to SYNC_STAGES loop
sync(i) <= sync(i - 1);
end loop;
-
+ sync2(1) <= not soft_res;
+ for i in 2 to SYNC_STAGES loop
+ sync2(i) <= sync2(i - 1);
+ end loop;
end if;
+
end process;
sys_res_n <= sync(SYNC_STAGES);
+soft_res_n <= sync2(SYNC_STAGES);
--init : process(all)
projects / calu.git / blobdiff