pipeline erste version mit 31bit shifter (kostet 7MHz und viele LEs)

[calu.git] / cpu / src / core_top.vhd

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index 7ec0743961062e2158db09df3d6cbbe669e657e8..f146d8d4855b42b36a6c7889fcdf834255efecb5 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -11,8 +11,7 @@ entity core_top is
                --System input pins
                        sys_clk : in std_logic;
                        sys_res : in std_logic;
-
-                       to_next_stage : out dec_op
+                       result : out gp_register_t
                        
                );
 
@@ -29,10 +28,23 @@ architecture behav of core_top is
                signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
                signal reg_wr_data_pin : gp_register_t;
                signal reg_we_pin : std_logic;
+               signal to_next_stage : dec_op;
 
 --             signal reg1_rd_data_pin : gp_register_t;
 --             signal reg2_rd_data_pin : gp_register_t;
 
+                 signal result_pin : gp_register_t;--reg
+                 signal result_addr_pin : gp_addr_t;--reg
+                 signal addr_pin : word_t; --memaddr
+                 signal data_pin : gp_register_t; --mem data --ureg
+                 signal alu_jump_pin : std_logic;--reg
+                 signal brpr_pin  : std_logic;  --reg
+                 signal wr_en_pin : std_logic;--regop --reg
+                 signal dmem_pin  : std_logic;--memop
+                 signal dmem_wr_en_pin : std_logic;
+                 signal hword_pin  : std_logic;
+                 signal byte_s_pin : std_logic;
+
 
 begin
 
@@ -83,17 +95,29 @@ begin
                        to_next_stage => to_next_stage
                );
 
+          exec_st : execute_stage
+                generic map('0')
+                port map(sys_clk, sys_res,to_next_stage, result_pin, result_addr_pin,addr_pin,
+                data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
+
+          writeback_st : writeback_stage
+                generic map('0', '1')
+                port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
+                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
+
                
 --init : process(all)
 
 --begin
-       jump_result_pin <= (others => '0');
-       alu_jump_bit_pin <= '0';
-       reg_w_addr_pin <= (others => '0');
-       reg_wr_data_pin <= (others => '0');
-       reg_we_pin <= '0';
+--     jump_result_pin <= (others => '0');
+--     alu_jump_bit_pin <= '0';
+--     reg_w_addr_pin <= (others => '0');
+--     reg_wr_data_pin <= (others => '0');
+--     reg_we_pin <= '0';
        
 --end process;
        
+       result <= result_pin;
 
 end behav;