instr mem durch case, fibonacci als programm, 7seg als extension geadded, resultat...

[calu.git] / cpu / src / core_top.vhd

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index fdd760f1b13e1c6a712eeaaf362d4a433030ec91..d81095c664d43b01cdaa528d893979df97c91434 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -15,7 +15,12 @@ entity core_top is
 --                     result : out gp_register_t;
 --                     reg_wr_data : out gp_register_t
                  -- uart
-                       bus_tx : out std_logic
+                       bus_tx : out std_logic;
+                       
+                       sseg0 : out std_logic_vector(0 to 6);
+                       sseg1 : out std_logic_vector(0 to 6);
+                       sseg2 : out std_logic_vector(0 to 6);
+                       sseg3 : out std_logic_vector(0 to 6)
                );
 
 end core_top;
@@ -116,7 +121,7 @@ begin
                 generic map('0', '1')
                 port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);