copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / core_pkg.vhd

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index 87cfcc6d6d9877899f1d76acaa34601931e66145..9ca6bb5de5bc24774e6df6f34c422b7fde6350f4 100644 (file)
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 
 use IEEE.std_logic_1164.all;
@@ -66,7 +87,7 @@ package core_pkg is
                --Data outputs
 --                     reg1_rd_data : out gp_register_t;
 --                     reg2_rd_data : out gp_register_t;
-                       branch_prediction_res : out instruction_word_t;
+                       branch_prediction_res : out instruction_addr_t;
                        branch_prediction_bit : out std_logic;
 
                        to_next_stage : out dec_op
@@ -127,7 +148,8 @@ package core_pkg is
                        RESET_VALUE : std_logic;
                        -- active logic value
                        LOGIC_ACT : std_logic;
-                       FPGATYPE : string
+                       FPGATYPE : string;
+                       CLK_BAUD : integer
                        );
        port(
                --System inputs
@@ -158,10 +180,10 @@ package core_pkg is
                        im_addr : out gp_register_t;
                        im_data : out gp_register_t;
                        
-                       sseg0 : out std_logic_vector(0 to 6);
-                       sseg1 : out std_logic_vector(0 to 6);
-                       sseg2 : out std_logic_vector(0 to 6);
-                       sseg3 : out std_logic_vector(0 to 6);
+                       --sseg0 : out std_logic_vector(0 to 6);
+                       --sseg1 : out std_logic_vector(0 to 6);
+                       --sseg2 : out std_logic_vector(0 to 6);
+                       --sseg3 : out std_logic_vector(0 to 6);
 
                        int_req : out interrupt_t