--System inputs
clk : in std_logic;
reset : in std_logic;
+ s_reset : in std_logic;
--Data inputs
jump_result : in instruction_addr_t;
prediction_result : in instruction_addr_t;
branch_prediction_bit : in std_logic;
alu_jump_bit : in std_logic;
+ int_req : in interrupt_t;
+ new_im_data_in : in std_logic;
+ im_addr : in gp_register_t;
+ im_data : in gp_register_t;
--Data outputs
instruction : out instruction_word_t;
- prog_cnt : out instruction_addr_t
+ prog_cnt : out instruction_addr_t;
+ -- debug
+ led2 : out std_logic
);
end component fetch_stage;
--Data outputs
-- reg1_rd_data : out gp_register_t;
-- reg2_rd_data : out gp_register_t;
- branch_prediction_res : out instruction_word_t;
+ branch_prediction_res : out instruction_addr_t;
branch_prediction_bit : out std_logic;
to_next_stage : out dec_op
-- active reset value
RESET_VALUE : std_logic;
-- active logic value
- LOGIC_ACT : std_logic
-
+ LOGIC_ACT : std_logic;
+ FPGATYPE : string;
+ CLK_BAUD : integer
);
port(
--System inputs
-- same here
bus_tx : out std_logic;
bus_rx : in std_logic;
+ new_im_data_out : out std_logic;
+ im_addr : out gp_register_t;
+ im_data : out gp_register_t;
sseg0 : out std_logic_vector(0 to 6);
sseg1 : out std_logic_vector(0 to 6);
sseg2 : out std_logic_vector(0 to 6);
- sseg3 : out std_logic_vector(0 to 6)
+ sseg3 : out std_logic_vector(0 to 6);
+
+ int_req : out interrupt_t
+
);
end component writeback_stage;