decode stage die erste

[calu.git] / cpu / src / core_pkg.vhd

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index 301a51792296413b233f0e39bb65b8f08d1af2e3..57abe47e3e4a45e77af38148166aca61a565e37c 100644 (file)
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -46,6 +46,18 @@ package core_pkg is
                --System inputs
                        clk : in std_logic;
                        reset : in std_logic;
+
+               --Data inputs
+                       instruction : in instruction_word_t;
+                       reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+                       reg_wr_data : in gp_register_t;
+                       reg_we : in std_logic;
+
+               --Data outputs
+                       reg1_rd_data : gp_register_t;
+                       reg2_rd_data : gp_register_t;
+                       branch_prediction_res : instruction_word_t;
+                       branch_prediction_bit : std_logic
                );
        end component decode_stage;
 
@@ -84,4 +96,32 @@ package core_pkg is
        end component writeback_stage;
 
 
+       type instruction_rec is record
+
+               predicates : std_logic_vector(3 downto 0);
+
+               opcode : opcode_t;
+
+               reg_dest_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+               reg_src1_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+               reg_src2_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+
+               immediate : std_logic_vector(WORD_WIDTH-1 downto 0);
+               displacement : std_logic_vector(DISPL_WIDTH-1 downto 0);
+
+               jmptype : std_logic_vector(1 downto 0);
+
+               carry, sreg_update, high_low, fill, signext, bp, arith, left_right : std_logic;
+
+       end record;
+
+
+       type read_through_write_rec is record
+
+               rtw_reg : gp_register_t;
+               rtw_reg1 : std_logic;
+               rtw_reg2 : std_logic;
+
+       end record;
+
 end package core_pkg;