fetch und decode kompilierbar, generelle tb, änderung in pkgs, eigene decoder entity

[calu.git] / cpu / src / core_pkg.vhd

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index 57abe47e3e4a45e77af38148166aca61a565e37c..335ffb6876eec9f85eb5eb2d1515d1522052c8b5 100644 (file)
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -12,7 +12,7 @@ package core_pkg is
                        -- active reset value
                        RESET_VALUE : std_logic;
                        -- active logic value
-                       LOGIC_ACT : std_logic;
+                       LOGIC_ACT : std_logic
                        
                        );
        port(
@@ -39,7 +39,7 @@ package core_pkg is
                        -- active reset value
                        RESET_VALUE : std_logic;
                        -- active logic value
-                       LOGIC_ACT : std_logic;
+                       LOGIC_ACT : std_logic
                        
                        );
        port(
@@ -54,27 +54,36 @@ package core_pkg is
                        reg_we : in std_logic;
 
                --Data outputs
-                       reg1_rd_data : gp_register_t;
-                       reg2_rd_data : gp_register_t;
-                       branch_prediction_res : instruction_word_t;
-                       branch_prediction_bit : std_logic
+                       reg1_rd_data : out gp_register_t;
+                       reg2_rd_data : out gp_register_t;
+                       branch_prediction_res : out instruction_word_t;
+                       branch_prediction_bit : out std_logic
                );
        end component decode_stage;
 
 
+       component decoder is
+
+       port(
+                       instruction : in instruction_word_t;
+                       instr_spl : out instruction_rec
+               
+               );
+
+       end component decoder;
 
        component execute_stage is
        generic (
                        -- active reset value
                        RESET_VALUE : std_logic;
                        -- active logic value
-                       LOGIC_ACT : std_logic;
+                       LOGIC_ACT : std_logic
                        
                        );
        port(
                --System inputs
                        clk : in std_logic;
-                       reset : in std_logic;
+                       reset : in std_logic
                );
        end component execute_stage;
 
@@ -85,43 +94,16 @@ package core_pkg is
                        -- active reset value
                        RESET_VALUE : std_logic;
                        -- active logic value
-                       LOGIC_ACT : std_logic;
+                       LOGIC_ACT : std_logic
                        
                        );
        port(
                --System inputs
                        clk : in std_logic;
-                       reset : in std_logic;
+                       reset : in std_logic
                );
        end component writeback_stage;
 
 
-       type instruction_rec is record
-
-               predicates : std_logic_vector(3 downto 0);
-
-               opcode : opcode_t;
-
-               reg_dest_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
-               reg_src1_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
-               reg_src2_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
-
-               immediate : std_logic_vector(WORD_WIDTH-1 downto 0);
-               displacement : std_logic_vector(DISPL_WIDTH-1 downto 0);
-
-               jmptype : std_logic_vector(1 downto 0);
-
-               carry, sreg_update, high_low, fill, signext, bp, arith, left_right : std_logic;
-
-       end record;
-
-
-       type read_through_write_rec is record
-
-               rtw_reg : gp_register_t;
-               rtw_reg1 : std_logic;
-               rtw_reg2 : std_logic;
-
-       end record;
 
 end package core_pkg;