copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / common_pkg.vhd

diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd
index 43603d29a9638626502ee2c9640678e2f3ed711c..fd61464b221b6e15b5776aebde663784e21f3f71 100755 (executable)
--- a/cpu/src/common_pkg.vhd
+++ b/cpu/src/common_pkg.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 
 use IEEE.std_logic_1164.all;
@@ -24,15 +45,18 @@ package common_pkg is
        constant REG_ZERO : gp_register_t := (others => '0');
 
        constant INSTR_ADDR_WIDTH       : INTEGER := 32;
-       constant PHYS_INSTR_ADDR_WIDTH  : INTEGER := 11;
+       constant PHYS_INSTR_ADDR_WIDTH  : INTEGER := 10;
+       constant ROM_INSTR_ADDR_WIDTH : INTEGER := 7;
        constant REG_ADDR_WIDTH         : INTEGER := 4;
-       constant DATA_ADDR_WIDTH        : INTEGER := 11;
+       constant DATA_ADDR_WIDTH        : INTEGER := 10;
        constant PHYS_DATA_ADDR_WIDTH   : INTEGER := 32;
        
        constant NUM_OP_OPT_WIDTH       : INTEGER := 6;
        constant COND_WIDTH : INTEGER := 4;
        constant DATA_END_ADDR          : integer := ((2**DATA_ADDR_WIDTH)-1);
 
+       constant ROM_USE : std_logic := '1';
+       constant RAM_USE : std_logic := '0';
        
        subtype instruction_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
        subtype instruction_addr_t is std_logic_vector(INSTR_ADDR_WIDTH-1 downto 0);
@@ -56,10 +80,12 @@ package common_pkg is
        constant HWORD_OPT : integer := 1;
        constant PUSH_OPT : integer := 1;
        constant LOW_HIGH_OPT : integer := 1;
+       constant DIRECT_JUMP_OPT : integer := 1;
        
        constant CARRY_OPT : integer := 2;
        constant BYTE_OPT : integer := 2;
        constant LDI_REPLACE_OPT : integer := 2;
+       constant PWREN_OPT : integer := 2;
 
        constant RIGHT_OPT : integer := 3;
        constant JMP_REG_OPT : integer := 3;
@@ -71,8 +97,14 @@ package common_pkg is
        
        type op_info_t is (ADDSUB_OP,AND_OP,OR_OP, XOR_OP,SHIFT_OP, LDST_OP, JMP_OP, JMP_ST_OP, STACK_OP);
        subtype op_opt_t is std_logic_vector(NUM_OP_OPT_WIDTH-1 downto 0);
+
+       type interrupt_t is (IDLE, UART);       
        
-       
+       constant UART_INT_EN_BIT : integer := 1;
+       constant GLOBAL_INT_EN_BIT : integer := 0;
+
+       constant UART_INT_VECTOR : std_logic_vector(PHYS_INSTR_ADDR_WIDTH-1 downto 0) := (0 => '1', others => '0');
+
        type instruction_rec is record
 
                predicates : std_logic_vector(3 downto 0);
@@ -89,7 +121,7 @@ package common_pkg is
 
                jmptype : std_logic_vector(1 downto 0);
 
-               high_low, fill, signext, bp: std_logic;
+               high_low, fill, signext, bp, int: std_logic;
 
                op_detail : op_opt_t;
                op_group : op_info_t;