+-- `Deep Thought', a softcore CPU implemented on a FPGA
+--
+-- Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+-- Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+-- Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+-- Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+-- Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+
library IEEE;
use IEEE.std_logic_1164.all;
constant REG_ZERO : gp_register_t := (others => '0');
constant INSTR_ADDR_WIDTH : INTEGER := 32;
- constant PHYS_INSTR_ADDR_WIDTH : INTEGER := 11;
+ constant PHYS_INSTR_ADDR_WIDTH : INTEGER := 10;
constant ROM_INSTR_ADDR_WIDTH : INTEGER := 7;
constant REG_ADDR_WIDTH : INTEGER := 4;
- constant DATA_ADDR_WIDTH : INTEGER := 11;
+ constant DATA_ADDR_WIDTH : INTEGER := 10;
constant PHYS_DATA_ADDR_WIDTH : INTEGER := 32;
constant NUM_OP_OPT_WIDTH : INTEGER := 6;
constant UART_INT_EN_BIT : integer := 1;
constant GLOBAL_INT_EN_BIT : integer := 0;
- constant UART_INT_VECTOR : std_logic_vector(PHYS_INSTR_ADDR_WIDTH-1 downto 0) := "00000000001"; --integer := 1;
+ constant UART_INT_VECTOR : std_logic_vector(PHYS_INSTR_ADDR_WIDTH-1 downto 0) := (0 => '1', others => '0');
type instruction_rec is record