fetch und decode kompilierbar, generelle tb, änderung in pkgs, eigene decoder entity

[calu.git] / cpu / src / common_pkg.vhd

diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd
index 46434bcf991648fa24da65974733342c8507c1b1..c54829bc81b60da2c7b2016ce8549af3c1daa33a 100644 (file)
--- a/cpu/src/common_pkg.vhd
+++ b/cpu/src/common_pkg.vhd
@@ -5,12 +5,20 @@ use IEEE.numeric_std.all;
 
 package common_pkg is
 
+
        
        constant WORD_WIDTH   : INTEGER := 32;
        constant HWORD_WIDTH  : INTEGER := 16;
        constant BYTE_WIDTH   : INTEGER :=  8;
        constant OPCODE_WIDTH : INTEGER :=  5;
        constant DISPL_WIDTH  : INTEGER := 15;
+
+       subtype byte_t is std_logic_vector(BYTE_WIDTH-1 downto 0);
+       subtype hword_t is std_logic_vector(HWORD_WIDTH-1 downto 0);
+       subtype word_t  is std_logic_vector(WORD_WIDTH-1 downto 0);
+
+       subtype gp_register_t is word_t;
+
        
        constant REG_ZERO : gp_register_t := (others => '0');
 
@@ -23,14 +31,10 @@ package common_pkg is
        constant NUM_OP_OPT_WIDTH       : INTEGER := 5;
        constant COND_WIDTH : INTEGER := 4;
 
-       subtype byte_t is std_logic_vector(BYTE_WIDTH-1 downto 0);
-       subtype hword_t is std_logic_vector(HWORD_WIDTH-1 downto 0);
-       subtype word_t  is std_logic_vector(WORD_WIDTH-1 downto 0);
        
        subtype instruction_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
        subtype instruction_addr_t is std_logic_vector(INSTR_ADDR_WIDTH-1 downto 0);
        
-       subtype gp_register_t is word_t;
        subtype gp_addr_t       is unsigned(REG_ADDR_WIDTH-1 downto 0);
        subtype data_ram_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
        subtype data_ram_addr_t is std_logic_vector(DATA_ADDR_WIDTH-1 downto 0);
@@ -53,13 +57,39 @@ package common_pkg is
        
        constant PSW_DISABLE : integer := 4;
        
-       
-       
-       
        type op_info_t is (ADDSUB_OP,AND_OP,OR_OP, XOR_OP,SHIFT_OP);
        subtype op_opt_rec is std_logic_vector(NUM_OP_OPT_WIDTH-1 downto 0);
        
-       type dec_op is
+       
+       type instruction_rec is record
+
+               predicates : std_logic_vector(3 downto 0);
+
+               opcode : opcode_t;
+
+               reg_dest_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+               reg_src1_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+               reg_src2_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+
+               immediate : std_logic_vector(WORD_WIDTH-1 downto 0);
+               displacement : std_logic_vector(DISPL_WIDTH-1 downto 0);
+
+               jmptype : std_logic_vector(1 downto 0);
+
+               carry, sreg_update, high_low, fill, signext, bp, arith, left_right : std_logic;
+
+       end record;
+
+
+       type read_through_write_rec is record
+
+               rtw_reg : gp_register_t;
+               rtw_reg1 : std_logic;
+               rtw_reg2 : std_logic;
+
+       end record;
+
+       type dec_op is record
                condition : condition_t;
                op_group : op_info_t;
                op_detail : op_opt_rec;
@@ -71,15 +101,18 @@ package common_pkg is
                saddr1 : gp_addr_t;
                saddr2 : gp_addr_t;
                
-               daddr   : gp_addr_t
+               daddr   : gp_addr_t;
                
-       end record dec_op;
+       end record;
+
+       
+       
        
        function inc(value : in std_logic_vector; constant by : in integer := 1) return std_logic_vector;
        function log2c(constant value : in integer range 0 to integer'high) return integer;
 end package common_pkg;
 
-package body common_pkg;
+package body common_pkg is
 
        function inc(value : in std_logic_vector; constant by : in integer := 1) return std_logic_vector is
        begin