constant REG_ADDR_WIDTH : INTEGER := 4;
constant DATA_ADDR_WIDTH : INTEGER := 32;
constant PHYS_DATA_ADDR_WIDTH : INTEGER := 32;
+
+ constant NUM_OP_OPT_WIDTH : INTEGER := 5;
+ constant COND_WIDTH : INTEGER := 4;
subtype byte_t is std_logic_vector(BYTE_WIDTH-1 downto 0);
subtype hword_t is std_logic_vector(HWORD_WIDTH-1 downto 0);
subtype data_ram_addr_t is std_logic_vector(DATA_ADDR_WIDTH-1 downto 0);
subtype opcode_t is std_logic_vector(OPCODE_WIDTH-1 downto 0);
+ subtype condition_t is std_logic_vector(COND_WIDTH-1 downto 0);
+
+ --Opcode consits of decoded group information type and option bits
+ --currently not complete, might need option increase too.
+ --IMMEDIATE always in right_operand (src2)
+
+ constant IMM_OPT : integer := 0;
+
+ constant SUB_OPT : integer := 1;
+ constant LOG_SHIFT : integer := 1;
+
+ constant CARRY_OPT : integer := 2;
+
+ constant LEFT_SHIFT : integer := 3;
+
+ constant PSW_DISABLE : integer := 4;
+
+
+
+
+ type op_info_t is (ADDSUB_OP,AND_OP,OR_OP, XOR_OP,SHIFT_OP);
+ subtype op_opt_rec is std_logic_vector(NUM_OP_OPT_WIDTH-1 downto 0);
+
+ type dec_op is
+ condition : condition_t;
+ op_group : op_info_t;
+ op_detail : op_opt_rec;
+ brpr : std_logic;
+
+ src1 : gp_register_t;
+ src2 : gp_register_t;
+
+ saddr1 : gp_addr_t;
+ saddr2 : gp_addr_t;
+
+ daddr : gp_addr_t
+
+ end record dec_op;
function inc(value : in std_logic_vector; constant by : in integer := 1) return std_logic_vector;
function log2c(constant value : in integer range 0 to integer'high) return integer;