copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / alu_b.vhd

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index bd78302391114d40298521a502406204c8dbd839..9ebf6c5b5e9dc333ceec76e1c8e0d7ada4f7a8e1 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
@@ -122,19 +143,14 @@ begin
        case op_group is
        when ADDSUB_OP =>
                result_v := add_result;
-               addr(DATA_ADDR_WIDTH + 2) <= '0';
        when AND_OP =>
                result_v := and_result;
-               addr(DATA_ADDR_WIDTH + 2) <= '0';
        when OR_OP =>
                result_v := or_result;
-               addr(DATA_ADDR_WIDTH + 2) <= '0';
        when XOR_OP =>
                result_v := xor_result;
-               addr(DATA_ADDR_WIDTH + 2) <= '0';
        when SHIFT_OP =>
                result_v := shift_result;
-               addr(DATA_ADDR_WIDTH + 2) <= '0';
    when LDST_OP =>
                 res_prod := '0';
                 mem_op := '1';
@@ -155,7 +171,6 @@ begin
 
                         res_prod := '1';
                         mem_op := '0';
-                                                               addr(DATA_ADDR_WIDTH + 2) <= '0';
                 end if;
                 if op_detail(ST_OPT) = '1' then
                         mem_en := '1';