copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / alu_b.vhd

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index a7374face2fa6497cad465f36a972af0acf01fcf..9ebf6c5b5e9dc333ceec76e1c8e0d7ada4f7a8e1 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
@@ -75,7 +96,11 @@ begin
        paddr <= (others =>'0');
        
        result_v.result := add_result.result;
-       prog_cnt_nxt := std_logic_vector(unsigned(prog_cnt)+1);
+       if (op_detail(DIRECT_JUMP_OPT) = '0') then
+               prog_cnt_nxt := std_logic_vector(unsigned(prog_cnt)+1);
+       else
+               prog_cnt_nxt := prog_cnt;
+       end if;
        case cond is
        when COND_NZERO =>
                cond_met := not(alu_state.status.zero);
@@ -146,7 +171,6 @@ begin
 
                         res_prod := '1';
                         mem_op := '0';
-                                                               addr(DATA_ADDR_WIDTH + 2) <= '0';
                 end if;
                 if op_detail(ST_OPT) = '1' then
                         mem_en := '1';
@@ -179,15 +203,15 @@ begin
                end if;
        when STACK_OP =>
                mem_op := '1';
-               pwr_en_v := '1';
+               pwr_en_v := op_detail(PWREN_OPT);
                if op_detail(PUSH_OPT) = '1' then
                        mem_en := '1';
                        pinc_v := '1';
                        res_prod := '0';
-                       addr <= pval_nxt;
-                       data <= left_o;
+                       addr <= pval;
+                       data <= left_operand;
                else
-                       addr <= std_logic_vector(unsigned(pval_nxt)-4);
+                       addr <= pval_nxt;
                end if;
                
        end case;