+-- `Deep Thought', a softcore CPU implemented on a FPGA
+--
+-- Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+-- Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+-- Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+-- Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+-- Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
case op_group is
when ADDSUB_OP =>
result_v := add_result;
- addr(DATA_ADDR_WIDTH + 3) <= '0';
when AND_OP =>
result_v := and_result;
- addr(DATA_ADDR_WIDTH + 3) <= '0';
when OR_OP =>
result_v := or_result;
- addr(DATA_ADDR_WIDTH + 3) <= '0';
when XOR_OP =>
result_v := xor_result;
- addr(DATA_ADDR_WIDTH + 3) <= '0';
when SHIFT_OP =>
result_v := shift_result;
- addr(DATA_ADDR_WIDTH + 3) <= '0';
when LDST_OP =>
res_prod := '0';
mem_op := '1';
res_prod := '1';
mem_op := '0';
- addr(DATA_ADDR_WIDTH + 3) <= '0';
end if;
if op_detail(ST_OPT) = '1' then
mem_en := '1';