variable res_prod : std_logic;\r
variable cond_met : std_logic;\r
variable mem_en : std_logic;
- variable mem_op : std_logic;\r
+ variable mem_op : std_logic;
+ variable alu_jmp : std_logic;\r
begin\r
result_v := alu_state;\r
\r
- result_v.result := add_result.result;\r
res_prod := '1';\r
mem_en := '0';
- mem_op := '0';\r
- addr <= add_result.result;
+ mem_op := '0';
+ alu_jump := '0';\r
+
left <= left_operand;
right <= right_operand;
addr <= add_result.result;
data <= right_operand;\r
- \r
+
+ result_v.result := add_result.result;
+\r
case cond is\r
when COND_NZERO =>\r
cond_met := not(alu_state.status.zero);\r
cond_met := '0';\r
when others => null;\r
end case;\r
- \r
+
+ cond_met := cond_met and (alu_state.alu_jmp xnor alu_state.brpr);
+\r
case op_group is\r
when ADDSUB_OP =>\r
result_v := add_result;\r
if op_detail(ST_OPT) = '1' then
right <= displacement;
mem_en := '1';
- end if;\r
+ end if;
+ when JMP_OP =>
+ if op_detail(JMP_REG_OPT) = '0' then
+ left <= prog_cnt;
+ end if;
+ result_v.alu_jmp := '1';
+ when JMP_ST_OP => null;\r
end case;\r
\r
\r
result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
result_v.mem_en := mem_en and cond_met;
result_v.mem_op := mem_op and cond_met;
+ result_v.alu_jmp := alu_jmp and cond_met;
\r
alu_result <= result_v;\r
\r