ram: reducing instr- and dataram

[calu.git] / cpu / src / alu_b.vhd

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index c9e832e9c9ed321c37360beea36476d66e57ad04..746fbc3489e85f38a74e287224d97e8e7f481b9d 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -75,7 +75,11 @@ begin
        paddr <= (others =>'0');
        
        result_v.result := add_result.result;
-       prog_cnt_nxt := std_logic_vector(unsigned(prog_cnt)+1);
+       if (op_detail(DIRECT_JUMP_OPT) = '0') then
+               prog_cnt_nxt := std_logic_vector(unsigned(prog_cnt)+1);
+       else
+               prog_cnt_nxt := prog_cnt;
+       end if;
        case cond is
        when COND_NZERO =>
                cond_met := not(alu_state.status.zero);
@@ -118,23 +122,40 @@ begin
        case op_group is
        when ADDSUB_OP =>
                result_v := add_result;
+               addr(DATA_ADDR_WIDTH + 3) <= '0';
        when AND_OP =>
                result_v := and_result;
+               addr(DATA_ADDR_WIDTH + 3) <= '0';
        when OR_OP =>
                result_v := or_result;
+               addr(DATA_ADDR_WIDTH + 3) <= '0';
        when XOR_OP =>
                result_v := xor_result;
+               addr(DATA_ADDR_WIDTH + 3) <= '0';
        when SHIFT_OP =>
                result_v := shift_result;
+               addr(DATA_ADDR_WIDTH + 3) <= '0';
    when LDST_OP =>
                 res_prod := '0';
                 mem_op := '1';
                --right_o <= displacement;
                addr <= std_logic_vector(unsigned(left_operand)+unsigned(displacement));
                 if op_detail(IMM_OPT) = '1' then
-                        result_v.result := right_operand;
+                                        
+                                                               result_v.result := right_operand;
+                                        
+                                                               if (op_detail(LDI_REPLACE_OPT) = '0') then
+                                                                       result_v.result := left_operand;
+                                                                       if (op_detail(LOW_HIGH_OPT) = '1') then
+                                                                               result_v.result(31 downto 16) := right_operand(31 downto 16);
+                                                                       else
+                                                                               result_v.result(15 downto 0) := right_operand(15 downto 0);
+                                                                       end if;
+                                                               end if;
+
                         res_prod := '1';
                         mem_op := '0';
+                                                               addr(DATA_ADDR_WIDTH + 3) <= '0';
                 end if;
                 if op_detail(ST_OPT) = '1' then
                         mem_en := '1';
@@ -167,15 +188,15 @@ begin
                end if;
        when STACK_OP =>
                mem_op := '1';
-               pwr_en_v := '1';
+               pwr_en_v := op_detail(PWREN_OPT);
                if op_detail(PUSH_OPT) = '1' then
                        mem_en := '1';
                        pinc_v := '1';
                        res_prod := '0';
-                       addr <= pval_nxt;
-                       data <= left_o;
+                       addr <= pval;
+                       data <= left_operand;
                else
-                       addr <= std_logic_vector(unsigned(pval_nxt)-4);
+                       addr <= pval_nxt;
                end if;
                
        end case;