static branch incl prediction rc1

[calu.git] / cpu / src / alu_b.vhd

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index 8399d6087e835d11d1375fc5a43e4c7d5bf10c27..696e0f798fb647394689a9e147b3e0522f0a3aa4 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -21,7 +21,7 @@ architecture behaviour of alu is
        );                      \r
        end component exec_op;\r
        \r
-       signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;
+       signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;\r
         signal left, right : gp_register_t;\r
        \r
 begin\r
@@ -41,28 +41,29 @@ begin
        shift_inst : entity work.exec_op(shift_op)\r
        port map(clk,reset,left, right, op_detail, alu_state, shift_result);\r
 \r
-calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
+calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr)\r
        variable result_v : alu_result_rec;\r
        variable res_prod : std_logic;\r
        variable cond_met : std_logic;\r
-       variable mem_en : std_logic;
-        variable mem_op : std_logic;
-       variable alu_jmp : std_logic;\r
+       variable mem_en : std_logic;\r
+        variable mem_op : std_logic;\r
+       variable alu_jump : std_logic;\r
+       variable nop     : std_logic;\r
 begin\r
        result_v := alu_state;\r
        \r
        res_prod := '1';\r
-       mem_en := '0';
-        mem_op := '0';
+       mem_en := '0';\r
+        mem_op := '0';\r
        alu_jump := '0';\r
-  
-        left <= left_operand;
-        right <= right_operand;
-
-        addr <= add_result.result;
+  \r
+        left <= left_operand;\r
+        right <= right_operand;\r
+\r
+        addr <= add_result.result;\r
         data <= right_operand;\r
-       
-       result_v.result := add_result.result;
+       \r
+       result_v.result := add_result.result;\r
 \r
        case cond is\r
        when COND_NZERO =>\r
@@ -99,8 +100,9 @@ begin
                cond_met := '0';\r
        when others => null;\r
        end case;\r
-       
-       cond_met := cond_met and (alu_state.alu_jmp xnor alu_state.brpr);
+       \r
+       nop := (alu_state.alu_jump xnor alu_state.brpr);\r
+       cond_met := cond_met and nop;\r
 \r
        case op_group is\r
        when ADDSUB_OP =>\r
@@ -112,24 +114,24 @@ begin
        when XOR_OP =>\r
                result_v := xor_result;\r
        when SHIFT_OP =>\r
-               result_v := shift_result;
-        when LDST_OP =>
-                res_prod := '0';
-                mem_op := '1';
-                if op_detail(IMM_OPT) = '1' then
-                        result_v.result := right_operand;
-                        res_prod := '1';
-                        mem_op := '0';
-                end if;
-                if op_detail(ST_OPT) = '1' then
-                        right <= displacement;
-                        mem_en := '1';
-                end if;
-       when JMP_OP =>
-               if op_detail(JMP_REG_OPT) = '0' then
-                       left <= prog_cnt;
-               end if;
-               result_v.alu_jmp := '1';
+               result_v := shift_result;\r
+        when LDST_OP =>\r
+                res_prod := '0';\r
+                mem_op := '1';\r
+                if op_detail(IMM_OPT) = '1' then\r
+                        result_v.result := right_operand;\r
+                        res_prod := '1';\r
+                        mem_op := '0';\r
+                end if;\r
+                if op_detail(ST_OPT) = '1' then\r
+                        right <= displacement;\r
+                        mem_en := '1';\r
+                end if;\r
+       when JMP_OP =>\r
+               if op_detail(JMP_REG_OPT) = '0' then\r
+                       left <= prog_cnt;\r
+               end if;\r
+               alu_jump := '1';\r
        when JMP_ST_OP => null;\r
        end case;\r
        \r
@@ -146,10 +148,17 @@ begin
        end if;\r
        \r
        result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
-       result_v.mem_en := mem_en and cond_met;
-        result_v.mem_op := mem_op and cond_met;
-       result_v.alu_jmp := alu_jmp and cond_met;
+       result_v.mem_en := mem_en and cond_met;\r
+        result_v.mem_op := mem_op and cond_met;\r
+       result_v.alu_jump := alu_jump and cond_met;\r
+       result_v.brpr := brpr and nop;\r
         \r
+       if (result_v.alu_jump = '0') and (brpr = '1') then\r
+               result_v.result := (others => '0');\r
+               result_v.result(prog_cnt'range) := std_logic_vector(unsigned(prog_cnt)+1);\r
+               --result_v.reg_op := '1';\r
+       end if;\r
+\r
        alu_result <= result_v;\r
        \r
 end process calc; \r