copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / alu.vhd

diff --git a/cpu/src/alu.vhd b/cpu/src/alu.vhd
index b94421acee0b5df956606d73b5914eca019cb654..c9e3aa20fa28b1f9cf2412737e66eddbdb7e9771 100755 (executable)
--- a/cpu/src/alu.vhd
+++ b/cpu/src/alu.vhd
@@ -1,9 +1,31 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA\r
+--\r
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>\r
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>\r
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>\r
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>\r
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>\r
+--\r
+--  This program is free software: you can redistribute it and/or modify\r
+--  it under the terms of the GNU General Public License as published by\r
+--  the Free Software Foundation, either version 3 of the License, or\r
+--  (at your option) any later version.\r
+--\r
+--  This program is distributed in the hope that it will be useful,\r
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+--  GNU General Public License for more details.\r
+--\r
+--  You should have received a copy of the GNU General Public License\r
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.\r
+\r
 library IEEE;\r
 use IEEE.std_logic_1164.all;\r
 use IEEE.numeric_std.all;\r
 \r
 use work.common_pkg.all;\r
 use work.alu_pkg.all;\r
+use work.extension_pkg.all;\r
 \r
 entity alu is\r
        --some modules won't need all inputs\r
@@ -13,13 +35,28 @@ entity alu is
                        clk : in std_logic;\r
                        reset : in std_logic;\r
        --operation inputs\r
-                       condition       :       condition_t;\r
+                       cond : in condition_t;\r
                        op_group : in op_info_t;\r
                        left_operand : in gp_register_t;\r
                        right_operand : in gp_register_t;\r
+                       \r
+            displacement : in gp_register_t;\r
+                       prog_cnt    : in instr_addr_t;\r
+                       brpr        : in std_logic;\r
+                       \r
                        op_detail : in op_opt_t;\r
+                       \r
                        alu_state  : in alu_result_rec;\r
-                       alu_result : out alu_result_rec\r
+                       pval            : in gp_register_t;\r
+                       pval_nxt    : in gp_register_t;\r
+                       \r
+                       alu_result : out alu_result_rec;\r
+            addr : out word_t; --memaddr\r
+            data : out gp_register_t; --mem data --ureg\r
+                       \r
+                       pinc : out std_logic;\r
+                       pwr_en : out std_logic;\r
+                       paddr : out paddr_t\r
                );\r
                \r
 end alu;\r