instruction memory progammer: is in and works in simulations

[calu.git] / cpu / sim / testcore1.do

diff --git a/cpu/sim/testcore1.do b/cpu/sim/testcore1.do
index f6b51b9ef364657a8ef4b4ab47df47c11d289a36..c781ad4b771bb90ef5d63dee70216a80a337845b 100644 (file)
--- a/cpu/sim/testcore1.do
+++ b/cpu/sim/testcore1.do
@@ -39,7 +39,13 @@ vcom -work work ../src/extension.vhd
 vcom -work work ../src/extension_b.vhd
 
 
+vcom -work work ../src/extension_imp_pkg.vhd
+vcom -work work ../src/extension_imp.vhd
+vcom -work work ../src/extension_imp_b.vhd
 
+vcom -work work ../src/extension_7seg_pkg.vhd
+vcom -work work ../src/extension_7seg.vhd
+vcom -work work ../src/extension_7seg_b.vhd
 
 vcom -work work ../src/extension_uart_pkg.vhd
 vcom -work work ../src/rs232_tx.vhd
@@ -124,25 +130,12 @@ add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writebac
 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_addr
 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/regfile_val
 
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/ram_data
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/ext_uart
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg_nxt
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/ext_reg
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w1_st_co_nxt
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w2_uart_config
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w3_uart_send
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w4_uart_receive
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/data_out
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/new_tx_data
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/bus_tx
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/tx_data
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/tx_rdy
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/tx_rdy_int
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/sys_clk
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/cnt
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/stop_bit
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/bd_rate
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/im_addr
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/im_data
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/new_im_data_out
+add wave  -group test -radix hexadecimal /pipeline_tb/fetch_st/im_addr
+add wave  -group test -radix hexadecimal /pipeline_tb/fetch_st/im_data
+add wave  -group test -radix hexadecimal /pipeline_tb/fetch_st/new_im_data_in
 
 
 run 5000 ns