add wave -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_rd_data
add wave -group fetchstageregister -radix hexadecimal /pipeline_tb/fetch_st/instruction
add wave -group fetchstage -format logic /pipeline_tb/fetch_st/branch_prediction_bit
+add wave -group fetchstage -format logic /pipeline_tb/fetch_st/rom_ram
add wave -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/prediction_result
add wave -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instruction
add wave -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_addr
add wave -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/regfile_val
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/im_addr
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/im_data
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/new_im_data_out
-add wave -group test -radix hexadecimal /pipeline_tb/fetch_st/im_addr
-add wave -group test -radix hexadecimal /pipeline_tb/fetch_st/im_data
-add wave -group test -radix hexadecimal /pipeline_tb/fetch_st/new_im_data_in
+add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/reg_we
+add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/write_en
+add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_en
+add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_write_en
+add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/ext_anysel
+add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/alu_jmp
+add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.address
run 5000 ns