instr mem durch case, fibonacci als programm, 7seg als extension geadded, resultat...
[calu.git] / cpu / sim / testcore.do
index 9a4c3fe0a01afc76ddc63d3c50b059284f037fd0..0b2647ea5bdaef865ad65abcd3af61fb465a8257 100644 (file)
@@ -6,17 +6,22 @@ vcom -work work ../src/r_w_ram.vhd
 vcom -work work ../src/r_w_ram_b.vhd
 vcom -work work ../src/r2_w_ram.vhd
 vcom -work work ../src/r2_w_ram_b.vhd
+vcom -work work ../src/rom.vhd
+vcom -work work ../src/rom_b.vhd
 vcom -work work ../src/common_pkg.vhd
+vcom -work work ../src/core_pkg.vhd
 vcom -work work ../src/extension_pkg.vhd
 vcom -work work ../src/extension_uart_pkg.vhd
 vcom -work work ../src/extension_uart.vhd
 vcom -work work ../src/extension_uart_b.vhd
+vcom -work work ../src/extension_7seg_pkg.vhd
+vcom -work work ../src/extension_7seg.vhd
+vcom -work work ../src/extension_7seg_b.vhd
 vcom -work work ../src/rs232_tx.vhd
 vcom -work work ../src/rs232_tx_arc.vhd
 vcom -work work ../src/rs232_rx.vhd
 vcom -work work ../src/rs232_rx_arc.vhd
 
-vcom -work work ../src/core_pkg.vhd
 vcom -work work ../src/decoder.vhd
 vcom -work work ../src/decoder_b.vhd
 vcom -work work ../src/fetch_stage.vhd