small bugfix in wb-stage

[calu.git] / cpu / create_project.tcl

diff --git a/cpu/create_project.tcl b/cpu/create_project.tcl
index 367e4a27aa5d9cc8ac36da3975706459d7fb2b3b..c2dc47b0e9dba54033faef02ede2f623af9d6c68 100755 (executable)
--- a/cpu/create_project.tcl
+++ b/cpu/create_project.tcl
@@ -34,6 +34,8 @@ if {$make_assignments} {
        set_global_assignment -name TOP_LEVEL_ENTITY core_top
        set_global_assignment -name VHDL_FILE ../src/core_top.vhd
        set_global_assignment -name VHDL_FILE ../src/mem_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../src/rom.vhd
+       set_global_assignment -name VHDL_FILE ../src/rom_b.vhd
        set_global_assignment -name VHDL_FILE ../src/r_w_ram.vhd
        set_global_assignment -name VHDL_FILE ../src/r_w_ram_b.vhd
        set_global_assignment -name VHDL_FILE ../src/r2_w_ram.vhd