library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.core_pkg.all;

architecture behav of writeback_stage is


begin

syn: process(sys_clk, reset)

begin

	if (reset = RESET_VALUE) then
				
	elsif rising_edge(sys_clk) then
		
	end if;
	
end process; 

end behav;