library ieee;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

architecture behaviour of rw_r_ram is

	subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
	type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
	
	signal ram : RAM_TYPE; --:= (others=> x"00");

begin
	process(clk)
	begin
		if rising_edge(clk) then
			if wr_en = '1' then
				ram(to_integer(UNSIGNED(rw_addr))) <= data_in;
				rw_out <= data_in;
			else
				rw_out <= ram(to_integer(UNSIGNED(rw_addr)));
			end if;
				rd_out <= ram(to_integer(UNSIGNED(rd_addr)));
		end if;
	end process;
end architecture behaviour;