--   `Deep Thought', a softcore CPU implemented on a FPGA
--
--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.

library ieee;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.common_pkg.all;
use work.mem_pkg.all;

architecture behaviour of ram_xilinx is
	type word_t is array (0 to 3) of std_logic_vector(7 downto 0);
	subtype stfu_t is std_logic_vector(BYTE_WIDTH-1 downto 0);
	type ram_t is array (0 to (2**ADDR_WIDTH)-1) of stfu_t;
	signal ram0 : ram_t := (others => x"00");
	signal ram1 : ram_t := (others => x"00");
	signal ram2 : ram_t := (others => x"00");
	signal ram3 : ram_t := (others => x"00");
	signal q_local : word_t;

begin -- Re-organize the read data from the RAM to match the output
	unpack: for i in 0 to 3 generate
		q(8*(i+1) - 1 downto 8*i) <= q_local(i);
	end generate unpack;

	process(clk)
	begin
		if(rising_edge(clk)) then
			if(we = '1') then
				if(be(0) = '1') then
					ram0(to_integer(UNSIGNED(waddr))) <= wdata(7 downto 0);
				end if;
				if be(1) = '1' then
					ram1(to_integer(UNSIGNED(waddr))) <= wdata(15 downto 8);
				end if;
				if be(2) = '1' then
					ram2(to_integer(UNSIGNED(waddr))) <= wdata(23 downto 16);
				end if;
				if be(3) = '1' then
					ram3(to_integer(UNSIGNED(waddr))) <= wdata(31 downto 24);
				end if;
			end if;
			q_local(0) <= ram0(to_integer(UNSIGNED(raddr)));
			q_local(1) <= ram1(to_integer(UNSIGNED(raddr)));
			q_local(2) <= ram2(to_integer(UNSIGNED(raddr)));
			q_local(3) <= ram3(to_integer(UNSIGNED(raddr)));
		end if;
	end process;
	
end architecture behaviour;