library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;

entity ram_xilinx is
	generic	(
				ADDR_WIDTH : integer range 1 to integer'high
			);
	port(
		clk : in std_logic;

		waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);

		be : in std_logic_vector (3 downto 0);
		
		we : in std_logic;

		wdata : in std_logic_vector(31 downto 0);
		
		q : out std_logic_vector(31 downto 0)
	);
end;