library ieee;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.mem_pkg.all;

architecture behaviour of r_w_ram is

	subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
	type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
	
									-- r0 = 0, r1 = 1, r2 = 3, r3 = A

	signal ram : RAM_TYPE := (  0 => "11100001000010001000000000111000", -- r1 = 7
				    1 => "11100001000100010000000000101000", -- r2 = 5
				    2 => "11100001000110011000000000100000", -- r3 = 4
				    3 => "11100000001000010001100000000000", -- r4 = r2 + r3
				    4 => "11100010001010100000100000000000", -- r5 = r4 and r1
				  others => x"F0000000");

--	signal ram : RAM_TYPE := (  0 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
--				    1 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
--				    2 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
--				    3 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
--				    4 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
--				    5 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
--				    6 => "11101100000000001000000000000000", --cmp r0 , r1       => 0-1 => 0100
--				    7 => "00000000001010101010000000000001", --addnqd r5, r5, r4 => r5 = 2
--				    8 => "00000000001010101010000000000000", --addnq r5, r5, r4  => r5 = 4
--				    9 => "11101100001000100000000000000000", --cmp r4 , r4       => 2-2 => 1001
--				   10 => "00000001001100001000000001010000", --addinq r6, r1, 0xA => nix
--				   11 => "00010001001100001000000001010000", --addieq r6, r1, 0xA => r6 = 0xB
--				   12 => "00010001101100110000000001010000", --subieq r6, r5, 0xA => r6 = 1
--				   13 => "11100000000100001000000000000000", --add r2, r1, r0     => r2 = 1
--				   14 => "11100010000100001000000000000000", --and r2, r1, r0     => r2 = 0
--				   15 => "11101100000000001000000000000000", --cmp r0 , r1        => 0-1 => 0100
--				   16 => "10000000001010101010000000000001", --addabd r5, r5, r4  => r5 = 6
--				   17 => "10110011101110001000010000110001", --orxltd r7, 1086    => r7 = 1086
--				   18 => "10110101001110001000010000000001", --shiftltd r7, r1, 1 => r7 = 2
--				   19 => "01010101001110001000100000000001", --shiftltd r7, r1, 2 => r7 = 4
--				  others => x"F0000000");


begin
	process(clk)
	begin
		if rising_edge(clk) then
			data_out <= ram(to_integer(UNSIGNED(rd_addr)));
			
			if wr_en = '1' then
				ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
			end if;
		end if;
	end process;
end architecture behaviour;