library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.common_pkg.all;
use work.core_pkg.all;

-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity pipeline_tb is

end pipeline_tb;


-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
architecture behavior of pipeline_tb is

	constant cc : time := 30 ns;        -- test clock period
	
		signal sys_clk_pin : std_logic;
		signal sys_res_n_pin : std_logic;
		--Data input
		
		signal dummy : std_logic;

		signal jump_result_pin : instruction_addr_t;
		signal prediction_result_pin : instruction_addr_t;
		signal branch_prediction_bit_pin : std_logic;
		signal alu_jump_bit_pin : std_logic;
		signal instruction_pin : instruction_word_t;

		signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
		signal reg_wr_data_pin : gp_register_t;
		signal reg_we_pin : std_logic;
		signal to_next_stage_pin : dec_op;

begin

--		instruction_ram : r_w_ram
--		generic map (
--			PHYS_INSTR_ADDR_WIDTH,
--			WORD_WIDTH
--		)
--		
--		port map (
--			sys_clk,
--			instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
--			instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
--			instr_we,
--			instr_wr_data,
--			instr_rd_data
--		);

	fetch_st : fetch_stage
		generic map (
	
			'0',
			'1'
		)
		
		port map (
		--System inputs
			clk => sys_clk_pin, --: in std_logic;
			reset => sys_res_n_pin, --: in std_logic;
		
		--Data inputs
			jump_result => jump_result_pin, --: in instruction_addr_t;
			prediction_result => prediction_result_pin, --: in instruction_addr_t;
			branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
			alu_jump_bit => alu_jump_bit_pin, --: in std_logic;

		--Data outputs
			instruction => instruction_pin --: out instruction_word_t
		);

	decode_st : decode_stage
		generic	map (
			-- active reset value
			'0',
			-- active logic value
			'1'
			
			)
		port map (
		--System inputs
			clk => sys_clk_pin, --: in std_logic;
			reset => sys_res_n_pin, -- : in std_logic;

		--Data inputs
			instruction => instruction_pin, --: in instruction_word_t;
			reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
			reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
			reg_we => reg_we_pin, --: in std_logic;

		--Data outputs
			branch_prediction_res => prediction_result_pin, --: instruction_word_t;
			branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
			to_next_stage => to_next_stage_pin
			
		);



-------------------------------------------------------------------------------
-- generate simulation clock
-------------------------------------------------------------------------------
  CLKGEN : process
  begin
    sys_clk_pin <= '1';
    wait for cc/2;
    sys_clk_pin <= '0';
    wait for cc/2;
  end process CLKGEN;
  
-------------------------------------------------------------------------------
-- test the design
-------------------------------------------------------------------------------
  TEST_IT : process

    -- wait for n clock cycles
    procedure icwait(cycles : natural) is
    begin
      for i in 1 to cycles loop
        wait until sys_clk_pin = '1' and sys_clk_pin'event;
      end loop;
    end;
	
  begin
    -----------------------------------------------------------------------------
    -- initial reset
    -----------------------------------------------------------------------------
	sys_res_n_pin <= '0';
	reg_w_addr_pin <= (others => '0');
	reg_wr_data_pin <= (others => '0');
	reg_we_pin <= '0';

	icwait(10);
	dummy <= '1';
	sys_res_n_pin <= '1';
	wait until sys_res_n_pin = '1';
	

	icwait(100000);

    ---------------------------------------------------------------------------
    -- exit testbench
    ---------------------------------------------------------------------------
    assert false
      report "Test finished"
      severity error;

  end process test_it;

end behavior;


-------------------------------------------------------------------------------
-- configuration
-------------------------------------------------------------------------------
configuration pipeline_conf_beh of pipeline_tb is
  for behavior
    for fetch_st : fetch_stage use entity work.fetch_stage(behav);
    end for;
    for decode_st : decode_stage use entity work.decode_stage(behav);
    end for;

  end for;
end pipeline_conf_beh;