-- `Deep Thought', a softcore CPU implemented on a FPGA -- -- Copyright (C) 2010 Markus Hofstaetter -- Copyright (C) 2010 Martin Perner -- Copyright (C) 2010 Stefan Rebernig -- Copyright (C) 2010 Manfred Schwarz -- Copyright (C) 2010 Bernhard Urban -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see . library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.common_pkg.all; use work.core_pkg.all; use work.extension_pkg.all; ------------------------------------------------------------------------------- -- ENTITY ------------------------------------------------------------------------------- entity pipeline_tb is end pipeline_tb; ------------------------------------------------------------------------------- -- ARCHITECTURE ------------------------------------------------------------------------------- architecture behavior of pipeline_tb is constant cc : time := 20 ns; -- test clock period constant SYS_CLOCK_FREQ : integer := 50000000; constant BAUD_COUNT : integer := SYS_CLOCK_FREQ/115200; signal sys_clk_pin : std_logic; signal sys_res_n_pin : std_logic; --Data input signal dummy : std_logic; signal jump_result_pin : instruction_addr_t; signal prediction_result_pin : instruction_addr_t; signal branch_prediction_bit_pin : std_logic; signal alu_jump_bit_pin : std_logic; signal instruction_pin : instruction_word_t; signal prog_cnt : instruction_addr_t; signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0); signal reg_wr_data_pin : gp_register_t; signal reg_we_pin : std_logic; signal to_next_stage_pin : dec_op; signal result_pin : gp_register_t;--reg signal result_addr_pin : gp_addr_t;--reg signal addr_pin : word_t; --memaddr signal data_pin : gp_register_t; --mem data --ureg signal alu_jump_pin : std_logic;--reg signal brpr_pin : std_logic; --reg signal wr_en_pin : std_logic;--regop --reg signal dmem_pin : std_logic;--memop signal dmem_wr_en_pin : std_logic; signal hword_pin : std_logic; signal byte_s_pin, tx_pin, rx_pin : std_logic; signal gpm_in_pin : extmod_rec; signal gpm_out_pin : gp_register_t; signal nop_pin : std_logic; signal cycle_cnt : integer; signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6); signal int_req_pin : interrupt_t; signal new_im_data :std_logic; signal im_addr, im_data : gp_register_t; begin -- instruction_ram : r_w_ram -- generic map ( -- PHYS_INSTR_ADDR_WIDTH, -- WORD_WIDTH -- ) -- -- port map ( -- sys_clk, -- instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0), -- instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0), -- instr_we, -- instr_wr_data, -- instr_rd_data -- ); fetch_st : fetch_stage generic map ( '0', '1' ) port map ( --System inputs clk => sys_clk_pin, --: in std_logic; reset => sys_res_n_pin, --: in std_logic; s_reset => '1', --Data inputs jump_result => jump_result_pin, --: in instruction_addr_t; prediction_result => prediction_result_pin, --: in instruction_addr_t; branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic; alu_jump_bit => alu_jump_bit_pin, --: in std_logic; new_im_data_in => new_im_data, im_addr => im_addr, im_data => im_data, --Data outputs instruction => instruction_pin, --: out instruction_word_t prog_cnt => prog_cnt, int_req => int_req_pin ); decode_st : decode_stage generic map ( -- active reset value '0', -- active logic value '1' ) port map ( --System inputs clk => sys_clk_pin, --: in std_logic; reset => sys_res_n_pin, -- : in std_logic; --Data inputs instruction => instruction_pin, --: in instruction_word_t; prog_cnt => prog_cnt, reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0); reg_wr_data => reg_wr_data_pin, --: in gp_register_t; reg_we => reg_we_pin, --: in std_logic; nop => nop_pin, --Data outputs branch_prediction_res => prediction_result_pin, --: instruction_word_t; branch_prediction_bit => branch_prediction_bit_pin, --: std_logic to_next_stage => to_next_stage_pin ); exec_st : execute_stage generic map('0') port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin, data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin); writeback_st : writeback_stage generic map('0', '1', "altera",50) port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req_pin); nop_pin <= (alu_jump_bit_pin);-- xor brpr_pin); ------------------------------------------------------------------------------- -- generate simulation clock ------------------------------------------------------------------------------- CLKGEN : process begin sys_clk_pin <= '1'; wait for cc/2; sys_clk_pin <= '0'; wait for cc/2; end process CLKGEN; cnt : process(sys_clk_pin, sys_res_n_pin) begin if (sys_res_n_pin = '0') then cycle_cnt <= 0; elsif (sys_clk_pin'event and sys_clk_pin = '1') then cycle_cnt <= cycle_cnt + 1; end if; end process cnt; ------------------------------------------------------------------------------- -- test the design ------------------------------------------------------------------------------- TEST_IT : process -- wait for n clock cycles procedure icwait(cycles : natural) is begin for i in 1 to cycles loop wait until sys_clk_pin = '1' and sys_clk_pin'event; end loop; end; procedure txd(trans_data : in std_logic_vector) is begin for i in 0 to 9 loop rx_pin <= trans_data(i); report "bit: " & std_logic'image(trans_data(i)); dummy <= not dummy; wait on dummy; -- icwait(BAUD_COUNT); icwait(50); end loop; end txd; begin ----------------------------------------------------------------------------- -- initial reset ----------------------------------------------------------------------------- sys_res_n_pin <= '0'; rx_pin <= '1'; -- reg_w_addr_pin <= (others => '0'); -- reg_wr_data_pin <= (others => '0'); -- reg_we_pin <= '0'; icwait(10); dummy <= '1'; sys_res_n_pin <= '1'; wait until sys_res_n_pin = '1'; icwait(10); txd("0000100101"); icwait(600); icwait(600); txd("0000100101"); icwait(600000000); --------------------------------------------------------------------------- -- exit testbench --------------------------------------------------------------------------- assert false report "Test finished" severity error; end process test_it; end behavior; ------------------------------------------------------------------------------- -- configuration ------------------------------------------------------------------------------- configuration pipeline_conf_beh of pipeline_tb is for behavior for fetch_st : fetch_stage use entity work.fetch_stage(behav); end for; for decode_st : decode_stage use entity work.decode_stage(behav); end for; for exec_st : execute_stage use entity work.execute_stage(behav); end for; for writeback_st : writeback_stage use entity work.writeback_stage(behav); end for; end for; end pipeline_conf_beh;