library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.common_pkg.all;
use work.extension_pkg.all;

package extension_uart_pkg is






--RS232
constant UART_WIDTH : integer := 8;
subtype uart_data is std_logic_vector(UART_WIDTH-1 downto 0);
constant BAUD_RATE_WIDTH : integer := 16;
subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0);
--CLKs
--constant CLK_FREQ_MHZ : real := 33.33;
--constant BAUD_RATE : integer := 115200;
--constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
constant CLK_PER_BAUD : integer := 434;

 component extension_uart is
        --some modules won't need all inputs/outputs
	generic	(
			-- active reset value
			RESET_VALUE : std_logic
			);
	port(
		--System inputs
			clk :   in std_logic;
			reset : in std_logic;
		-- general extension interface			
			ext_reg  : in extmod_rec;
			data_out : out gp_register_t;

			uart_int : out std_logic;
		-- Input
			bus_rx : in std_logic;
		-- Ouput
			bus_tx : out std_logic
		);
 end component extension_uart;

component rs232_tx is
	generic	(
		-- active reset value
		RESET_VALUE : std_logic
		);

	port(
		--System inputs
		sys_clk : in std_logic;
		sys_res_n : in std_logic;

		--Bus
		bus_tx : out std_logic;

		--From/to sendlogic
		new_tx_data : in std_logic;
		tx_data : in uart_data;
		tx_rdy : out std_logic;
		bd_rate : in baud_rate_l;
		stop_bit : in std_logic	
);
end component rs232_tx;

component rs232_rx is
	generic	(
		-- active reset value
		RESET_VALUE : std_logic;
		SYNC_STAGES : integer range 2 to integer'high
		);

	port(
		--System inputs
		sys_clk : in std_logic;
		sys_res_n : in std_logic;

		--Bus
		bus_rx_unsync : in std_logic;

		--To sendlogic
		new_rx_data : out std_logic;
		rx_data : out uart_data;
		bd_rate : in baud_rate_l
	);
end component rs232_rx;



end package extension_uart_pkg;