--   `Deep Thought', a softcore CPU implemented on a FPGA
--
--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

use work.common_pkg.all;
use work.core_pkg.all;


use work.mem_pkg.all;
use work.extension_pkg.all;
use work.extension_timer_pkg.all;

architecture behav of extension_timer is

signal w1_st_co, w1_st_co_nxt, w2_im_val, w2_im_val_nxt : gp_register_t;
signal w3_im_notused, w3_im_notused_nxt, w4_im_notused, w4_im_notused_nxt : gp_register_t;

begin

syn : process (clk, reset)
begin
   if (reset = RESET_VALUE) then
			w1_st_co <= (others => '0');
			w2_im_val <= (others => '0');
			w3_im_notused <= (others => '0');
			w4_im_notused <= (others => '0');
	elsif rising_edge(clk) then
			w1_st_co <= w1_st_co_nxt;
			w2_im_val <= w2_im_val_nxt;
			w3_im_notused <= w3_im_notused_nxt;
			w4_im_notused <= w4_im_notused_nxt;
   end if;
end process syn;

-------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------

gwriten : process (ext_reg, w1_st_co, w2_im_val, w3_im_notused, w4_im_notused)
variable tmp_data : gp_register_t;
begin
	w1_st_co_nxt <= w1_st_co;
	w2_im_val_nxt <= w2_im_val;
	w3_im_notused_nxt <= w3_im_notused;
	w4_im_notused_nxt <= w4_im_notused;

	-- timer logic
	if (w1_st_co(0) = '1') then -- timer enabled?
		w2_im_val_nxt <= std_logic_vector(IEEE.numeric_std.unsigned(w2_im_val) + 1);
		-- n00b overflow (logic elements sparen...)
		if(w2_im_val(31) = '1') then 
			w1_st_co_nxt(16) <= '1';
		end if;
	end if;

	if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
		tmp_data := (others =>'0');			
		for i in 0 to 3 loop
			if ext_reg.byte_en(i) = '1' then
				tmp_data(((i+1)*byte_t'length-1) downto i*byte_t'length) := ext_reg.data(((i+1)*byte_t'length-1) downto i*byte_t'length);
			end if;
		end loop;

		case ext_reg.addr(1 downto 0) is
		when "00" => -- status/config
			w1_st_co_nxt <= tmp_data;
		when "01" => -- timer value
			w2_im_val_nxt <= tmp_data;
		when "10" => null;
		when "11" => null;
		when others => null;
		end case;
	end if;
end process gwriten;

gread : process (clk, ext_reg, w1_st_co, w2_im_val, w3_im_notused, w4_im_notused)
variable tmp_data : gp_register_t;
begin
	tmp_data := (others => '0');
	if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
		case ext_reg.addr(1 downto 0) is
		when "00" => put_word_be(tmp_data, w1_st_co, ext_reg.byte_en);
		when "01" => put_word_be(tmp_data, w2_im_val, ext_reg.byte_en);
		when "10" => put_word_be(tmp_data, w3_im_notused, ext_reg.byte_en);
		when "11" => put_word_be(tmp_data, w4_im_notused, ext_reg.byte_en);
		when others => null;
		end case;
	end if;
	data_out <= tmp_data;
end process gread;

-------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
-------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
-------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------
end behav;