--   `Deep Thought', a softcore CPU implemented on a FPGA
--
--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.common_pkg.all;
use work.extension_pkg.all;

architecture behav of extension_interrupt is

signal w1_st_co, w1_st_co_nxt, w2_int_config, w2_int_config_nxt : gp_register_t;

begin

syn : process (clk, reset)
begin
   if (reset = RESET_VALUE) then
			w1_st_co <= (others=>'0');
			w2_int_config(31 downto 0) <= (others=>'0');
			-- todo mit einer konstante versehen

	elsif rising_edge(clk) then            
			w1_st_co <= w1_st_co_nxt;
			w2_int_config <= w2_int_config_nxt;
   end if;
end process syn;

-------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------

gwriten : process (ext_reg,w1_st_co,w2_int_config)

variable tmp_data  : gp_register_t;

begin

	w1_st_co_nxt <= w1_st_co;
	w2_int_config_nxt <= w2_int_config;

	if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
		tmp_data := (others =>'0');			
		if ext_reg.byte_en(0) = '1' then
			tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
		end if;
		if ext_reg.byte_en(1) = '1' then
			tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
		end if;
		if ext_reg.byte_en(2) = '1' then
			tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
		end if;
		if ext_reg.byte_en(3) = '1' then
			tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
		end if;

		case ext_reg.addr(1 downto 0) is
		when "00" => 
			w1_st_co_nxt <= tmp_data;
		when "01" =>
			w2_int_config_nxt <= tmp_data;
		when others => null;
		end case;
	end if;
	
end process gwriten;

gread : process (clk,ext_reg,w1_st_co,w2_int_config)

variable tmp_data  : gp_register_t;

begin

	if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
		case ext_reg.addr(1 downto 0) is
		when "00" => 
			tmp_data := (others =>'0');			
			if ext_reg.byte_en(0) = '1' then
				tmp_data(byte_t'range) := w1_st_co(byte_t'range);
			end if;
			if ext_reg.byte_en(1) = '1' then
				tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
			end if;
			if ext_reg.byte_en(2) = '1' then
				tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
			end if;
			if ext_reg.byte_en(3) = '1' then
				tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
			end if;
			data_out <= tmp_data;
		when "01" =>
			tmp_data := (others =>'0');			
			if ext_reg.byte_en(0) = '1' then
				tmp_data(byte_t'range) := w2_int_config(byte_t'range);
			end if;
			if ext_reg.byte_en(1) = '1' then
				tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_int_config((2*byte_t'length-1) downto byte_t'length);
			end if;
			if ext_reg.byte_en(2) = '1' then
				tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_int_config((3*byte_t'length-1) downto 2*byte_t'length);
			end if;
			if ext_reg.byte_en(3) = '1' then
				tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_int_config((4*byte_t'length-1) downto 3*byte_t'length);
			end if;
			data_out <= tmp_data;
		when others => data_out <= (others => '0');
		end case;
	else
		data_out  <= (others=>'0');		
	end if;
end process gread;


-------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------

-------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------

dataprocess : process (w2_int_config, uart_int)

begin

	int_req <= IDLE;

	if (w2_int_config(GLOBAL_INT_EN_BIT) = '1') then
		if (w2_int_config(UART_INT_EN_BIT) = '1' and uart_int = '1') then
			int_req <= UART;
		end if;
	end if;

end process dataprocess;



-------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------

end behav;