library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.common_pkg.all;
use work.core_pkg.all;

use work.mem_pkg.all;
use work.extension_pkg.all;

architecture behav of extension_gpm is
type gpm_internal is record
        status : status_rec;
	preg : pointers_t;
end record gpm_internal;

signal reg, reg_nxt : gpm_internal;


begin
syn : process (clk, reset)
begin
        if (reset = RESET_VALUE) then
                reg.status <= ('0','0','0','0');
		reg.pointers <= (others => (std_logic_vector(to_unsigned(DATA_END_ADDR,DATA_ADDR_WIDTH)));
        elsif rising_edge(clk) then
                reg <= reg_nxt;
        end if;
end process syn;

asyn : process (clk, reset, reg, alu_nxt, ext_reg, pval, pwr_en, pinc, paddr)
	variable reg_nxt_v : gpm_internal;
	variable incb : gp_register_t;
	variable sel_pval : gp_register_t;
begin
	reg_nxt_v := reg;

	psw <= reg.status;
	data_out <= (others => '0');

	incb := (others => '0');
	incb(0) := '1';
	if pinc = '1' then
		incb := (others => '1');
	end if;

	if (ext_reg.sel = '1') and ext_reg.wr_en = '1' then
		case ext_reg.addr(1 downto 0) is
		when "00" => 
			if ext_reg.byte_en(0) = '1' then
				reg_nxt_v.psw := (ext_reg.data(0),ext_reg.data(1),ext_reg.data(3),ext_reg.data(2));
				psw <= reg_nxt_v.psw;
			end if;
		when "01" =>
			--STACK_POINTER
			if ext_reg.byte_en(0) = '1' then
				reg_next_v.preg(0)(byte_t'range) := ext_reg.data(byte_t'range);
			end if;
			if ext_reg.byte_en(1) = '1' then
				reg_next_v.preg(0)((byte_t'length*2)-1 downto byte_t'length) :=
					ext_reg.data((byte_t'length*2)-1 downto byte_t'length) ;
			end if;
			if ext_reg.byte_en(2) = '1' then
				reg_next_v.preg(0)((byte_t'length*3)-1 downto byte_t'length*2) :=
					ext_reg.data((byte_t'length*3)-1 downto byte_t'length*2) ;
			end if;
			if ext_reg.byte_en(3) = '1' then
				reg_next_v.preg(0)((byte_t'length*4)-1 downto byte_t'length*3) :=
					ext_reg.data((byte_t'length*4)-1 downto byte_t'length*3) ;
			end if;
		when others => null;
		end case;
	end if;

	if (ext_reg.sel = '1') and wr_en = '0' then
		case ext_reg.addr(1 downto 0) is
		when "00" => 
			if ext_reg.byte_en(0) = '1' then
				data_out(3 downto 0) <= (reg.status.sign, reg.status.carry, reg.status.oflo, reg.status.zero);
			end if;
		when "01" =>
			--STACK_POINTER
			if ext_reg.byte_en(0) = '1' then
				data_out(byte_t'range) <= reg.preg(0)(byte_t'range);
			end if;
			if ext_reg.byte_en(1) = '1' then
				data_out((byte_t'length*2)-1 downto byte_t'length) <=
					reg_preg(0)((byte_t'length*2)-1 downto byte_t'length) ;
			end if;
			if ext_reg.byte_en(2) = '1' then
				data_out((byte_t'length*3)-1 downto 2*byte_t'length) <=
					reg_preg(0)((byte_t'length*3)-1 downto 2*byte_t'length) ;
			end if;
			if ext_reg.byte_en(3) = '1' then
				data_out((byte_t'length*4)-1 downto 3*byte_t'length) <=
					reg_preg(0)((byte_t'length*4)-1 downto 3*byte_t'length) ;
			end if;
		when others => null;
		end case;
	end if;


	sel_pval := reg_nxt_v.preg(unsigned(paddr));
	pval <= sel_pval;
	if pwr_en = '1' then
		reg_nxt_v.preg(to_integer(unsigned(paddr))) := std_logic_vector(unsigned(sel_pval)+unsigned(incb));
	end if;

	reg_nxt_v.status := alu_nxt.status;
 	
	reg_nxt <= reg_nxt_v;
end process asyn;

end behav;