--   `Deep Thought', a softcore CPU implemented on a FPGA
--
--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.common_pkg.all;
use work.extension_pkg.all;

package extension_7seg_pkg is

	constant SEGMENT_G : std_logic_vector(0 to 6) := "0000001";
	constant SEGMENT_F : std_logic_vector(0 to 6) := "0000010";
	constant SEGMENT_E : std_logic_vector(0 to 6) := "0000100";
	constant SEGMENT_D : std_logic_vector(0 to 6) := "0001000";
	constant SEGMENT_C : std_logic_vector(0 to 6) := "0010000";
	constant SEGMENT_B : std_logic_vector(0 to 6) := "0100000";
	constant SEGMENT_A : std_logic_vector(0 to 6) := "1000000";

	constant DIGIT_0 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_B or SEGMENT_C or SEGMENT_D or SEGMENT_E or SEGMENT_F;
	constant DIGIT_1 : std_logic_vector(0 to 6) := SEGMENT_B or SEGMENT_C;
	constant DIGIT_2 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_B or SEGMENT_G or SEGMENT_E or SEGMENT_D;
	constant DIGIT_3 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_B or SEGMENT_C or SEGMENT_D or SEGMENT_G;
	constant DIGIT_4 : std_logic_vector(0 to 6) := SEGMENT_B or SEGMENT_C or SEGMENT_G or SEGMENT_F;	
	constant DIGIT_5 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_F or SEGMENT_G or SEGMENT_C or SEGMENT_D;
	constant DIGIT_6 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_F or SEGMENT_E or SEGMENT_D or SEGMENT_C or SEGMENT_G;
	constant DIGIT_7 : std_logic_vector(0 to 6) := SEGMENT_A or DIGIT_1;
	constant DIGIT_8 : std_logic_vector(0 to 6) := SEGMENT_G or DIGIT_0;
	constant DIGIT_9 : std_logic_vector(0 to 6) := SEGMENT_B or DIGIT_5;
	constant DIGIT_A : std_logic_vector(0 to 6) := DIGIT_1 or SEGMENT_A or SEGMENT_G or SEGMENT_E or SEGMENT_F;
	constant DIGIT_B : std_logic_vector(0 to 6) := SEGMENT_F or SEGMENT_E or SEGMENT_D or SEGMENT_C or SEGMENT_G;
	constant DIGIT_C : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_F or SEGMENT_E or SEGMENT_D;
	constant DIGIT_D : std_logic_vector(0 to 6) := SEGMENT_B or SEGMENT_G or SEGMENT_E or SEGMENT_D or SEGMENT_C;
	constant DIGIT_E : std_logic_vector(0 to 6) := DIGIT_C or SEGMENT_G;
	constant DIGIT_F : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_F or SEGMENT_E or SEGMENT_G;
	constant DIGIT_MINUS : std_logic_vector(0 to 6) := SEGMENT_G;
	constant DIGIT_CLEAR : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_B or SEGMENT_C or SEGMENT_D or SEGMENT_E or SEGMENT_F or SEGMENT_G;
	
	subtype sseg_digit is std_logic_vector(4 downto 0);

	type sseg_state_rec is record
		digit0 : std_logic_vector(0 to 6);
		digit1 : std_logic_vector(0 to 6);
		digit2 : std_logic_vector(0 to 6);
		digit3 : std_logic_vector(0 to 6);
	end record;
	
	function digit_decode(value : sseg_digit) return std_logic_vector;
	
	component extension_7seg
	
	generic(
			RESET_VALUE : std_logic
		);
	port(
		--System inputs
			sys_clk : in std_logic;
			sys_res_n : in std_logic;
		-- general extension interface			
			ext_reg  : in extmod_rec;
--			data_out : out gp_register_t;
		--Control input
--			val : in std_logic_vector(4 downto 0);
--			pos : in std_logic_vector(1 downto 0);
--			act : std_logic;
		--Output
			o_digit0 : out std_logic_vector(0 to 6);
			o_digit1 : out std_logic_vector(0 to 6);
			o_digit2 : out std_logic_vector(0 to 6);
			o_digit3 : out std_logic_vector(0 to 6)
		);
	end component extension_7seg;
	
end extension_7seg_pkg;

package body extension_7seg_pkg is
	
	function digit_decode(value : sseg_digit) return std_logic_vector is
	
	begin
		case value is
			when "00000" => return DIGIT_0;
			when "00001" => return DIGIT_1;
			when "00010" => return DIGIT_2;
			when "00011" => return DIGIT_3;
			when "00100" => return DIGIT_4;
			when "00101" => return DIGIT_5;
			when "00110" => return DIGIT_6;
			when "00111" => return DIGIT_7;
			when "01000" => return DIGIT_8;
			when "01001" => return DIGIT_9;
			when "01010" => return DIGIT_A;
			when "01011" => return DIGIT_B;
			when "01100" => return DIGIT_C;
			when "01101" => return DIGIT_D;
			when "01110" => return DIGIT_E;
			when "01111" => return DIGIT_F;
			when "10000" => return "1111111";
			--when "11111" => return DIGIT_MINUS;
			when OTHERS => return DIGIT_CLEAR;
		end case;
	
	end function digit_decode;

end extension_7seg_pkg;