library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.common_pkg.all;
use work.extension_pkg.all;
use work.extension_7seg_pkg.all;

entity extension_7seg is

	generic(
			RESET_VALUE : std_logic
		);
	port(
		--System inputs
			sys_clk : in std_logic;
			sys_res_n : in std_logic;
		-- general extension interface			
			ext_reg  : in extmod_rec;
--			data_out : out gp_register_t;
		--Control input
--			val : in std_logic_vector(4 downto 0);
--			pos : in std_logic_vector(1 downto 0);
--			act : std_logic;
		--Output
			o_digit0 : out std_logic_vector(0 to 6);
			o_digit1 : out std_logic_vector(0 to 6);
			o_digit2 : out std_logic_vector(0 to 6);
			o_digit3 : out std_logic_vector(0 to 6)
		);
		
end extension_7seg;