--   `Deep Thought', a softcore CPU implemented on a FPGA
--
--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.common_pkg.all;
use work.extension_pkg.all;
use work.extension_7seg_pkg.all;

entity extension_7seg is

	generic(
			RESET_VALUE : std_logic
		);
	port(
		--System inputs
			sys_clk : in std_logic;
			sys_res_n : in std_logic;
		-- general extension interface			
			ext_reg  : in extmod_rec;
--			data_out : out gp_register_t;
		--Control input
--			val : in std_logic_vector(4 downto 0);
--			pos : in std_logic_vector(1 downto 0);
--			act : std_logic;
		--Output
			o_digit0 : out std_logic_vector(0 to 6);
			o_digit1 : out std_logic_vector(0 to 6);
			o_digit2 : out std_logic_vector(0 to 6);
			o_digit3 : out std_logic_vector(0 to 6)
		);
		
end extension_7seg;