library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.common_pkg.all;
use work.alu_pkg.all;

architecture behav of execute_stage is

signal condition : condition_t;
signal op_group : op_info_t;
signal op_detail : op_opt_t;
signal left_operand, right_operand : gp_register_t;
signal alu_state, alu_nxt : alu_result_rec;

signal psw : status_rec;

begin

alu_inst : alu
port map(clk, reset, condition, op_group, 
        op_detail, left_operand, right_operand, alu_state, alu_nxt);

syn: process(sys_clk, reset)

begin

	if (reset = RESET_VALUE) then
	        condition <=			
	elsif rising_edge(sys_clk) then
		
	end if;
	
end process;

asyn: process(reset,condition)
begin

        condition <= dec_instr.condition;
        op_group <= dec_instr.op_group;
        op_detail <= dec_instr.op_detail;
        left_operand <= dec_instr.src1;
        right_operand <= dec_instr.src2;

        alu_state.status <= psw;
        alu_state.result_addr <= dec_instr.daddr;
        alu_state.brpr <= brpr;
        alu_state.reg_op <= '0';
        alu_state.mem_op <= '0';
        alu_state.

        if reset = RESET_VALUE then
                condition <= COND_NEVER;
        else
                
        end if;

end process asyn;

end behav;