--   `Deep Thought', a softcore CPU implemented on a FPGA
--
--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.common_pkg.all;
use work.core_pkg.all;
use work.extension_pkg.all;

entity core_top is

	port(
		--System input pins
		   sys_res : in std_logic;
			soft_res : in std_logic;
			sys_clk : in std_logic;
--			result : out gp_register_t;
--			reg_wr_data : out gp_register_t
		  -- uart
			bus_tx : out std_logic;
			bus_rx : in std_logic;
			led1 : out std_logic;
			led2 : out std_logic;
			
			sseg0 : out std_logic_vector(0 to 6);
			sseg1 : out std_logic_vector(0 to 6);
			sseg2 : out std_logic_vector(0 to 6);
			sseg3 : out std_logic_vector(0 to 6)
		);

end core_top;

architecture behav of core_top is

		constant SYNC_STAGES : integer := 2;
		constant RESET_VALUE : std_logic := '0';

		signal jump_result : instruction_addr_t;
		signal jump_result_pin : instruction_addr_t;
		signal prediction_result_pin : instruction_addr_t;
		signal branch_prediction_bit_pin : std_logic;
		signal alu_jump_bit_pin : std_logic;
		signal instruction_pin : instruction_word_t;
		signal prog_cnt_pin : instruction_addr_t;

		signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
		signal reg_wr_data_pin : gp_register_t;
		signal reg_we_pin : std_logic;
		signal to_next_stage : dec_op;

--		signal reg1_rd_data_pin : gp_register_t;
--		signal reg2_rd_data_pin : gp_register_t;

                 signal result_pin : gp_register_t;--reg
                 signal result_addr_pin : gp_addr_t;--reg
                 signal addr_pin : word_t; --memaddr
                 signal data_pin : gp_register_t; --mem data --ureg
                 signal alu_jump_pin : std_logic;--reg
                 signal brpr_pin  : std_logic;  --reg
                 signal wr_en_pin : std_logic;--regop --reg
                 signal dmem_pin  : std_logic;--memop
                 signal dmem_wr_en_pin : std_logic;
                 signal hword_pin  : std_logic;
                 signal byte_s_pin : std_logic;
				 
		 signal gpm_in_pin : extmod_rec;
		 signal gpm_out_pin : gp_register_t;
		 signal nop_pin : std_logic;
		 
		 signal sync, sync2 : std_logic_vector(1 to SYNC_STAGES);
		 signal sys_res_n, soft_res_n : std_logic;
		 signal xilinxfail : std_logic;

		 signal int_req : interrupt_t;

		 signal new_im_data : std_logic;
		 signal im_addr, im_data : gp_register_t;

		 signal vers, vers_nxt : exec2wb_rec;
begin

	fetch_st : fetch_stage
		generic map (
	
			'0',
			'1'
		)
		
		port map (
		--System inputs
			clk => sys_clk, --: in std_logic;
			reset => sys_res_n, --: in std_logic;
			s_reset => soft_res_n,
		--Data inputs
			jump_result => jump_result_pin, --: in instruction_addr_t;
			prediction_result => prediction_result_pin, --: in instruction_addr_t;
			branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
			alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
			int_req => int_req,
		-- instruction memory program port :D
			new_im_data_in => new_im_data,
			im_addr => im_addr,
			im_data => im_data,
		--Data outputs
			instruction => instruction_pin, --: out instruction_word_t
			prog_cnt => prog_cnt_pin,
			led2 => led2
		);

	decode_st : decode_stage
		generic	map (
			-- active reset value
			'0',
			-- active logic value
			'1'
			
			)
		port map (
		--System inputs
			clk => sys_clk, --: in std_logic;
			reset => xilinxfail, -- : in std_logic;

		--Data inputs
			instruction => instruction_pin, --: in instruction_word_t;
			prog_cnt => prog_cnt_pin,
			reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
			reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
			reg_we => reg_we_pin, --: in std_logic;
			nop => nop_pin,

		--Data outputs
			branch_prediction_res => prediction_result_pin, --: instruction_word_t;
			branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
			to_next_stage => to_next_stage
		);

          exec_st : execute_stage
                generic map('0')
                port map(sys_clk, xilinxfail,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
                data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);


			vers_nxt.result <= result_pin;
			vers_nxt.result_addr <= result_addr_pin;
			vers_nxt.address <= addr_pin;
			vers_nxt.ram_data <= data_pin;
			vers_nxt.alu_jmp <= alu_jump_pin;
			vers_nxt.br_pred <= brpr_pin;
			vers_nxt.write_en <= wr_en_pin;
			vers_nxt.dmem_en <= dmem_pin;
			vers_nxt.dmem_write_en <= dmem_wr_en_pin;
			vers_nxt.hword <= hword_pin;
			vers_nxt.byte_s <= byte_s_pin;
									 
--          writeback_st : writeback_stage
--                generic map('0', '1')
--                port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
--                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
--                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
--

			writeback_st : writeback_stage
                generic map('0', '1', "s3e", 434)
                port map(sys_clk, xilinxfail, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
                vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
				-- instruction memory program port :D
				new_im_data, im_addr, im_data,
				-- sseg0, sseg1, sseg2, sseg3,
				int_req);


syn: process(sys_clk, sys_res)

begin

	if sys_res = '1' then
		led1 <= '0';
--			vers.result <= (others => '0');
--			vers.result_addr <= (others => '0');
--			vers.address <= (others => '0');
--			vers.ram_data <= (others => '0');
--			vers.alu_jmp <= '0';
--			vers.br_pred <= '0';
--			vers.write_en <= '0';
--			vers.dmem_en <= '0';
--			vers.dmem_write_en <= '0';
--			vers.hword <= '0';
--			vers.byte_s <= '0';
	
		sync <= (others => '0');
		sync2 <= (others => '0');
	
	elsif rising_edge(sys_clk) then
		led1 <= '1';
--		vers <= vers_nxt;
			sync(1) <= not sys_res;
			for i in 2 to SYNC_STAGES loop
				sync(i) <= sync(i - 1);
			end loop;
			sync2(1) <= not soft_res;
			for i in 2 to SYNC_STAGES loop
				sync2(i) <= sync2(i - 1);
			end loop;
	end if;
	
end process;

sys_res_n <= sync(SYNC_STAGES);
soft_res_n <= sync2(SYNC_STAGES);
xilinxfail <= sys_res_n and soft_res_n;
	
--init : process(all)

--begin
--	jump_result_pin <= (others => '0');
--	alu_jump_bit_pin <= '0';
--	reg_w_addr_pin <= (others => '0');
--	reg_wr_data_pin <= (others => '0');
--	reg_we_pin <= '0';
	
--end process;
	
--	result <= result_pin;
	nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);

	jump_result <= prog_cnt_pin; --jump_result_pin;
--	sys_res <= '1';

--	reg_wr_data <= reg_wr_data_pin;

end behav;