# Copyright (C) 1991-2010 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.

# Quartus II: Generate Tcl File for Project
# File: de1_cyclone_fmax.tcl
# Generated on: Mon Dec 20 19:47:21 2010

# Load Quartus II Tcl Project package
package require ::quartus::project

set need_to_close_project 0
set make_assignments 1

# Check that the right project is open
if {[is_project_open]} {
	if {[string compare $quartus(project) "de1_cyclone"]} {
		puts "Project de1_cyclone is not open"
		set make_assignments 0
	}
} else {
	# Only open if not already open
	if {[project_exists de1_cyclone]} {
		project_open -revision de1_cyclone de1_cyclone
	} else {
		project_new -revision de1_cyclone de1_cyclone
	}
	set need_to_close_project 1
}

# Make assignments
if {$make_assignments} {
	set_global_assignment -name FAMILY "Cyclone II"
	set_global_assignment -name DEVICE EP2C20F484C7
	set_global_assignment -name TOP_LEVEL_ENTITY core_top
	set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1"
	set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:41:06  DECEMBER 20, 2010"
	set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
	set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
	set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
	set_global_assignment -name MISC_FILE de1_cyclone.dpf
	set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
	set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
	set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
	set_global_assignment -name VHDL_FILE ../src/core_top.vhd
	set_global_assignment -name VHDL_FILE ../src/mem_pkg.vhd
	set_global_assignment -name VHDL_FILE ../src/r_w_ram.vhd
	set_global_assignment -name VHDL_FILE ../src/r_w_ram_b.vhd
	set_global_assignment -name VHDL_FILE ../src/r_w_ram_be.vhd
	set_global_assignment -name VHDL_FILE ../src/r_w_ram_be_b.vhd
	set_global_assignment -name VHDL_FILE ../src/rom.vhd
	set_global_assignment -name VHDL_FILE ../src/rom_b.vhd
	set_global_assignment -name VHDL_FILE ../src/r2_w_ram.vhd
	set_global_assignment -name VHDL_FILE ../src/r2_w_ram_b.vhd
	set_global_assignment -name VHDL_FILE ../src/common_pkg.vhd
	set_global_assignment -name VHDL_FILE ../src/core_pkg.vhd
	set_global_assignment -name VHDL_FILE ../src/fetch_stage.vhd
	set_global_assignment -name VHDL_FILE ../src/fetch_stage_b.vhd
	set_global_assignment -name VHDL_FILE ../src/decoder.vhd
	set_global_assignment -name VHDL_FILE ../src/decoder_b.vhd
	set_global_assignment -name VHDL_FILE ../src/decode_stage.vhd
	set_global_assignment -name VHDL_FILE ../src/decode_stage_b.vhd
	set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
	set_global_assignment -name VHDL_FILE ../src/extension_uart_pkg.vhd
	set_global_assignment -name VHDL_FILE ../src/extension_uart.vhd
	set_global_assignment -name VHDL_FILE ../src/extension_uart_b.vhd
	set_global_assignment -name VHDL_FILE ../src/rs232_tx.vhd
	set_global_assignment -name VHDL_FILE ../src/rs232_tx_arc.vhd
	set_global_assignment -name VHDL_FILE ../src/rs232_rx.vhd
	set_global_assignment -name VHDL_FILE ../src/rs232_rx_arc.vhd
	set_global_assignment -name VHDL_FILE ../src/extension_7seg_pkg.vhd
	set_global_assignment -name VHDL_FILE ../src/extension_7seg.vhd
	set_global_assignment -name VHDL_FILE ../src/extension_7seg_b.vhd
	set_global_assignment -name VHDL_FILE ../src/alu_pkg.vhd
	set_global_assignment -name VHDL_FILE ../src/extension.vhd
	set_global_assignment -name VHDL_FILE ../src/extension_b.vhd
	set_global_assignment -name VHDL_FILE ../src/exec_op.vhd
	set_global_assignment -name VHDL_FILE ../src/exec_op/add_op_b.vhd
	set_global_assignment -name VHDL_FILE ../src/exec_op/and_op_b.vhd
	set_global_assignment -name VHDL_FILE ../src/exec_op/or_op_b.vhd
	set_global_assignment -name VHDL_FILE ../src/exec_op/xor_op_b.vhd
	set_global_assignment -name VHDL_FILE ../src/exec_op/shift_op_b.vhd
	set_global_assignment -name VHDL_FILE ../src/alu.vhd
	set_global_assignment -name VHDL_FILE ../src/alu_b.vhd
	set_global_assignment -name VHDL_FILE ../src/execute_stage.vhd
	set_global_assignment -name VHDL_FILE ../src/execute_stage_b.vhd
	set_global_assignment -name VHDL_FILE ../src/writeback_stage.vhd
	set_global_assignment -name VHDL_FILE ../src/writeback_stage_b.vhd
	set_global_assignment -name FMAX_REQUIREMENT "80 MHz" -section_id sys_clk
	set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
	set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
	set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
	set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
	set_global_assignment -name SMART_RECOMPILE ON
	set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
	set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
	set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
	set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
	set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
	set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
	set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
	set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
	set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
	set_global_assignment -name MUX_RESTRUCTURE OFF
	set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
	set_location_assignment PIN_L1 -to sys_clk
	set_location_assignment PIN_R22 -to sys_res
	set_location_assignment PIN_G12 -to bus_tx
	set_location_assignment PIN_F14 -to bus_rx
	set_location_assignment PIN_J2 -to sseg0[0]
	set_location_assignment PIN_J1 -to sseg0[1]
	set_location_assignment PIN_H2 -to sseg0[2]
	set_location_assignment PIN_H1 -to sseg0[3]
	set_location_assignment PIN_F2 -to sseg0[4]
	set_location_assignment PIN_F1 -to sseg0[5]
	set_location_assignment PIN_E2 -to sseg0[6]
	set_location_assignment PIN_E1 -to sseg1[0]
	set_location_assignment PIN_H6 -to sseg1[1]
	set_location_assignment PIN_H5 -to sseg1[2]
	set_location_assignment PIN_H4 -to sseg1[3]
	set_location_assignment PIN_G3 -to sseg1[4]
	set_location_assignment PIN_D2 -to sseg1[5]
	set_location_assignment PIN_D1 -to sseg1[6]
	set_location_assignment PIN_G5 -to sseg2[0]
	set_location_assignment PIN_G6 -to sseg2[1]
	set_location_assignment PIN_C2 -to sseg2[2]
	set_location_assignment PIN_C1 -to sseg2[3]
	set_location_assignment PIN_E3 -to sseg2[4]
	set_location_assignment PIN_E4 -to sseg2[5]
	set_location_assignment PIN_D3 -to sseg2[6]
	set_location_assignment PIN_F4 -to sseg3[0]
	set_location_assignment PIN_D5 -to sseg3[1]
	set_location_assignment PIN_D6 -to sseg3[2]
	set_location_assignment PIN_J4 -to sseg3[3]
	set_location_assignment PIN_L8 -to sseg3[4]
	set_location_assignment PIN_F3 -to sseg3[5]
	set_location_assignment PIN_D4 -to sseg3[6]
	set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
	set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

	# Commit assignments
	export_assignments

	# Close project
	if {$need_to_close_project} {
		project_close
	}
}