.data .text .define UART_BASE, 0x2000 .define UART_STATUS, 0x0 .define UART_RECV, 0xc .define UART_TRANS, 0x8 .define UART_TRANS_EMPTY, 0x1 .define UART_RECV_NEW, 0x2 .define PBASE, 0x2030 .define PADDR, 0x4 .define PDATA, 0x8 ;----- start: br+ main br+ main ret main: ldi r10, UART_BASE@lo ldih r10, UART_BASE@hi ldi r11, PBASE@lo ldih r11, PBASE@hi poll: ldw r3, UART_STATUS(r10) andx r3, UART_RECV_NEW brzs+ poll; branch if zero call recv_byte ; we received the enter bootrom sign xor r1, r1, r1 cmpi r0, 0x48 ; 'H' breq- bt_H br poll ; else ;----- send_byte: ldw r3, UART_STATUS(r10) andx r3, UART_TRANS_EMPTY brnz+ send_byte ; branch if not zero stb r1, UART_TRANS(r10) ret ;----- send_word: lrs r0, r1, 0 call send_byte lrs r0, r1, 8 call send_byte lrs r0, r1, 16 call send_byte lrs r0, r1, 24 call send_byte ret ;----- recv_byte: ldw r3, UART_STATUS(r10) andx r3, UART_RECV_NEW brzs+ recv_byte; branch if zero xor r0, r0, r0 ldb r0, UART_RECV(r10) ret ;----- recv_word: xor r1, r1, r1 call recv_byte or r1, r0, r1 call recv_byte lls r1, r1, 8 or r1, r0, r1 call recv_byte lls r1, r1, 8 or r1, r0, r1 call recv_byte lls r1, r1, 8 or r1, r0, r1 addi r0, r1, 0 ret ;----- bootrom: call recv_byte br tehend xor r1, r1, r1 cmpi r0, 0x57 ; 'W' breq- bt_W cmpi r0, 0x52 ; 'R' breq- bt_R cmpi r0, 0x51 ; 'Q' breq- bt_Q cmpi r0, 0x54 ; 'T' breq- bt_T cmpi r0, 0x4a ; 'J' breq- bt_J ; cmpi r0, 0x48 ; 'H' ; breq bt_H ; FALL THROUGH ;) bt_H: ldi r1, 0x4f ; 'O' call send_byte call send_byte br bootrom bt_W: call recv_word ; receive addr stw r0, PADDR(r11) call recv_word ; receive instr stw r0, PDATA(r11) ldi r1, 0x44 ; 'D' call send_byte br bootrom bt_R: call recv_word ; receive addr mov r2, r0 ldi r1, 0x46 ; 'F' call send_byte ldx r1, 0(r2) call send_word br bootrom bt_Q: call recv_word ; receive addr mov r6, r0 call recv_word ; receive data stw r0, 0(r6) ldi r1, 0x41 ; 'A' call send_byte br bootrom bt_T: call recv_word ; receive addr mov r2, r0 ldi r1, 0x47 ; 'G' call send_byte ldw r1, 0(r2) call send_word br bootrom bt_J: call recv_word brr r0 tehend: