\section{Comparison}

\subsection{Description of the ISA}
\begin{itemize}
	\item The ISA describe a register machine.
	\item It is a RISC architecture.
	\item All latencies are handled in the hardware and are not visible to the ISA level.
	\item Conditional branches are unbundled, a branch only checks if the flags for the conditions are set properly.
	\item In an FPGA :)
	\item Be fast enough, to be faster than the other groups.
	\item Predicated instructions, 16-bit immediates for logical instruction.
	\item at the moment we are not aware of anything that we would like to change.
\end{itemize}

\subsection{Aim}
Our approach was to cherry pick the best features, which can be easily implemented, of the ISA we compared in task 1.
We took the predicated instructions like ARM is using them, static branch prediction which is used in PowerPC and extension modules like SPEAR2 uses.

\subsection{Listing}
\lstinputlisting[caption=sum Code]{src/sum.s}
The Loop contains five instructions with each one cycle execution-time. The codesize is 20 Bytes because each instruction is 32-Bits big.