-/* vm/jit/powerpc/arch.h - architecture defines for PowerPC
+/* src/vm/jit/powerpc/arch.h - architecture defines for PowerPC
- Copyright (C) 1996-2005 R. Grafl, A. Krall, C. Kruegel, C. Oates,
- R. Obermaisser, M. Platter, M. Probst, S. Ring, E. Steiner,
- C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich, J. Wenninger,
- Institut f. Computersprachen - TU Wien
+ Copyright (C) 1996-2010
+ CACAOVM - Verein zur Foerderung der freien virtuellen Maschine CACAO
This file is part of CACAO.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
- 02111-1307, USA.
-
- Contact: cacao@complang.tuwien.ac.at
-
- Authors: Christian Thalinger
-
- $Id: arch.h 1887 2005-01-27 11:29:56Z twisti $
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA.
*/
#ifndef _ARCH_H
#define _ARCH_H
+#define JIT_COMPILER_VIA_SIGNAL
+
+#include "config.h"
-/* preallocated registers *****************************************************/
-/* integer registers */
-
-#define REG_RESULT 3 /* to deliver method results */
-#define REG_RESULT2 4 /* to deliver long method results */
+/* define architecture features ***********************************************/
-/*#define REG_RA 26*/ /* return address */
-#define REG_PV 13 /* procedure vector, must be provided by caller */
-#define REG_METHODPTR 12 /* pointer to the place from where the procedure */
- /* vector has been fetched */
-#define REG_ITMP1 11 /* temporary register */
-#define REG_ITMP2 12 /* temporary register and method pointer */
-#define REG_ITMP3 0 /* temporary register */
+#define SUPPORT_DIVISION 1
+#define SUPPORT_LONG 1
-#define REG_ITMP1_XPTR 11 /* exception pointer = temporary register 1 */
-#define REG_ITMP2_XPC 12 /* exception pc = temporary register 2 */
+#define SUPPORT_I2F 0
+#define SUPPORT_I2D 0
+#define SUPPORT_L2F 0
+#define SUPPORT_L2D 0
-#define REG_SP 1 /* stack pointer */
-#define REG_ZERO 0 /* allways zero */
+#define SUPPORT_F2I 1
+#define SUPPORT_F2L 0
+#define SUPPORT_D2I 1
+#define SUPPORT_D2L 0
-/* floating point registers */
+#define SUPPORT_LONG_ADD 1
+#define SUPPORT_LONG_CMP 0
+#define SUPPORT_LONG_CMP_CONST 1
+#define SUPPORT_LONG_LOGICAL 1
+#define SUPPORT_LONG_SHIFT 0
+#define SUPPORT_LONG_MUL 0
+#define SUPPORT_LONG_DIV 0
-#define REG_FRESULT 1 /* to deliver floating point method results */
-#define REG_FTMP1 16 /* temporary floating point register */
-#define REG_FTMP2 17 /* temporary floating point register */
-#define REG_FTMP3 0 /* temporary floating point register */
+#define SUPPORT_LONG_DIV_POW2 0
+#define SUPPORT_LONG_REM_POW2 0
-#define REG_IFTMP 0 /* temporary integer and floating point register */
+#define SUPPORT_CONST_LOGICAL 1 /* AND, OR, XOR with immediates */
+#define SUPPORT_CONST_MUL 1 /* mutiply with immediate */
+#define SUPPORT_CONST_STORE 0 /* do we support const stores */
+#define SUPPORT_CONST_STORE_ZERO_ONLY 0 /* on some risc machines we can */
+ /* only store REG_ZERO */
-/*#define INT_SAV_CNT 19*/ /* number of int callee saved registers */
-#define INT_ARG_CNT 8 /* number of int argument registers */
-/*#define FLT_SAV_CNT 18*/ /* number of flt callee saved registers */
-#define FLT_ARG_CNT 13 /* number of flt argument registers */
+/* float **********************************************************************/
-#define TRACE_ARGS_NUM 8
+#define SUPPORT_FLOAT 1
+#if defined(ENABLE_SOFT_FLOAT_CMP)
+# define SUPPORT_FLOAT_CMP 0
+#else
+# define SUPPORT_FLOAT_CMP 1
+#endif
-/* define architecture features ***********************************************/
-#define POINTERSIZE 4
-#define WORDS_BIGENDIAN 1
+/* double *********************************************************************/
-#define U8_AVAILABLE 1
+#define SUPPORT_DOUBLE 1
-#define USE_CODEMMAP 1
+#if defined(ENABLE_SOFT_FLOAT_CMP)
+# define SUPPORT_DOUBLE_CMP 0
+#else
+# define SUPPORT_DOUBLE_CMP 1
+#endif
-#define SUPPORT_DIVISION 0
-#define SUPPORT_LONG 1
-#define SUPPORT_FLOAT 1
-#define SUPPORT_DOUBLE 1
-#define SUPPORT_FMOD 0
-#define SUPPORT_FICVT 1
-#define SUPPORT_IFCVT 0
+#define SPECIALMEMUSE
-#define SUPPORT_LONG_ADD 1
-#define SUPPORT_LONG_CMP 1
-#define SUPPORT_LONG_LOG 1
-#define SUPPORT_LONG_SHIFT 0
-#define SUPPORT_LONG_MUL 0
-#define SUPPORT_LONG_DIV 0
-#define SUPPORT_LONG_ICVT 0
-#define SUPPORT_LONG_FCVT 0
+/* Memory Positions for not Interface Stackslots (allocate_scratch_registers)*/
+/* are not properly aligned in case HAS_4_BYTE_STACKSLOT is not defined! */
+/* For HAS_4_BYTE_STACKSLOT archs no distinction is made between long and dbl*/
+#define SUPPORT_COMBINE_INTEGER_REGISTERS
-#define SUPPORT_LOGICAL_CONST 1 /* AND, OR, XOR with immediates */
-#define SUPPORT_CONST_ASTORE 0 /* do we support const astores */
-#define SUPPORT_ONLY_ZERO_ASTORE 1 /* on risc machines we can only store */
- /* REG_ZERO */
+/* branches *******************************************************************/
-#define USEBUILTINTABLE
+#define SUPPORT_BRANCH_CONDITIONAL_CONDITION_REGISTER 1
+#define SUPPORT_BRANCH_CONDITIONAL_ONE_INTEGER_REGISTER 0
+#define SUPPORT_BRANCH_CONDITIONAL_TWO_INTEGER_REGISTERS 0
-/* #define CONDITIONAL_LOADCONST */
-#define NOLONG_CONDITIONAL
-/* #define CONSECUTIVE_INTARGS */
-#define CONSECUTIVE_FLOATARGS
+/* exceptions *****************************************************************/
-#define SPECIALMEMUSE
-#define USETWOREGS
+#define SUPPORT_HARDWARE_DIVIDE_BY_ZERO 0
+
+
+/* stackframe *****************************************************************/
+
+#define STACKFRMAE_RA_BETWEEN_FRAMES 0
+#define STACKFRAME_RA_TOP_OF_FRAME 0
+#define STACKFRAME_RA_LINKAGE_AREA 1
+#define STACKFRAME_LEAFMETHODS_RA_REGISTER 1
+#define STACKFRAME_SYNC_NEEDS_TWO_SLOTS 1
+
+
+/* replacement ****************************************************************/
+
+#define REPLACEMENT_PATCH_SIZE 4 /* bytes */
+
+/* subtype ********************************************************************/
+
+#define USES_NEW_SUBTYPE 1
#endif /* _ARCH_H */
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