/* src/vm/jit/powerpc/arch.h - architecture defines for PowerPC
- Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
- C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
- E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
- J. Wenninger, Institut f. Computersprachen - TU Wien
+ Copyright (C) 1996-2010
+ CACAOVM - Verein zur Foerderung der freien virtuellen Maschine CACAO
This file is part of CACAO.
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
02110-1301, USA.
- Contact: cacao@cacaojvm.org
-
- Authors: Christian Thalinger
-
- Changes:
-
- $Id: arch.h 4357 2006-01-22 23:33:38Z twisti $
-
*/
#ifndef _ARCH_H
#define _ARCH_H
-/* define architecture features ***********************************************/
+#define JIT_COMPILER_VIA_SIGNAL
-#define U8_AVAILABLE 1
+#include "config.h"
-#define USEBUILTINTABLE
+
+/* define architecture features ***********************************************/
#define SUPPORT_DIVISION 1
#define SUPPORT_LONG 1
-#define SUPPORT_FLOAT 1
-#define SUPPORT_DOUBLE 1
#define SUPPORT_I2F 0
#define SUPPORT_I2D 0
#define SUPPORT_LONG_MUL 0
#define SUPPORT_LONG_DIV 0
+#define SUPPORT_LONG_DIV_POW2 0
+#define SUPPORT_LONG_REM_POW2 0
+
#define SUPPORT_CONST_LOGICAL 1 /* AND, OR, XOR with immediates */
#define SUPPORT_CONST_MUL 1 /* mutiply with immediate */
#define SUPPORT_CONST_STORE_ZERO_ONLY 0 /* on some risc machines we can */
/* only store REG_ZERO */
-/* #define CONDITIONAL_LOADCONST 1 */
+
+/* float **********************************************************************/
+
+#define SUPPORT_FLOAT 1
+
+#if defined(ENABLE_SOFT_FLOAT_CMP)
+# define SUPPORT_FLOAT_CMP 0
+#else
+# define SUPPORT_FLOAT_CMP 1
+#endif
+
+
+/* double *********************************************************************/
+
+#define SUPPORT_DOUBLE 1
+
+#if defined(ENABLE_SOFT_FLOAT_CMP)
+# define SUPPORT_DOUBLE_CMP 0
+#else
+# define SUPPORT_DOUBLE_CMP 1
+#endif
+
#define SPECIALMEMUSE
-#define HAS_4BYTE_STACKSLOT
+
+/* Memory Positions for not Interface Stackslots (allocate_scratch_registers)*/
+/* are not properly aligned in case HAS_4_BYTE_STACKSLOT is not defined! */
+/* For HAS_4_BYTE_STACKSLOT archs no distinction is made between long and dbl*/
#define SUPPORT_COMBINE_INTEGER_REGISTERS
+
+/* branches *******************************************************************/
+
+#define SUPPORT_BRANCH_CONDITIONAL_CONDITION_REGISTER 1
+#define SUPPORT_BRANCH_CONDITIONAL_ONE_INTEGER_REGISTER 0
+#define SUPPORT_BRANCH_CONDITIONAL_TWO_INTEGER_REGISTERS 0
+
+
+/* exceptions *****************************************************************/
+
+#define SUPPORT_HARDWARE_DIVIDE_BY_ZERO 0
+
+
+/* stackframe *****************************************************************/
+
+#define STACKFRMAE_RA_BETWEEN_FRAMES 0
+#define STACKFRAME_RA_TOP_OF_FRAME 0
+#define STACKFRAME_RA_LINKAGE_AREA 1
+#define STACKFRAME_LEAFMETHODS_RA_REGISTER 1
+#define STACKFRAME_SYNC_NEEDS_TWO_SLOTS 1
+
+
+/* replacement ****************************************************************/
+
+#define REPLACEMENT_PATCH_SIZE 4 /* bytes */
+
+/* subtype ********************************************************************/
+
+#define USES_NEW_SUBTYPE 1
+
#endif /* _ARCH_H */