PR157: ARM memory barrier

[cacao.git] / src / vm / jit / arm / md-atomic.hpp

diff --git a/src/vm/jit/arm/md-atomic.hpp b/src/vm/jit/arm/md-atomic.hpp
index 81f0a3926ac8f0db71fe027c9cae9d66a1ed226d..c6bb4e9096d962b6a1149fc5db0f2e88ad691dda 100644 (file)
--- a/src/vm/jit/arm/md-atomic.hpp
+++ b/src/vm/jit/arm/md-atomic.hpp
@@ -32,43 +32,16 @@
 
 #include "threads/atomic.hpp"
 
-
-/**
- * An atomic compare and swap for 32-bit integer values.
- *
- * @param p      Pointer to memory address.
- * @param oldval Old value to be expected.
- * @param newval New value to be stored.
- *
- * @return value of the memory location before the store
+/* Apparently, this is the best way to define a memory barrier on Linux.
+ * See for example: http://icedtea.classpath.org/hg/icedtea6/file/7c7835fceadc/ports/hotspot/src/os_cpu/linux_zero/vm/orderAccess_linux_zero.inline.hpp#l29
  */
-inline uint32_t Atomic::compare_and_swap(volatile uint32_t *p, uint32_t oldval, uint32_t newval)
-{
-       uint32_t result;
-       uint32_t temp;
-
-       /* TODO: improve this one! */
-       __asm__ __volatile__ (
-               "1:\t"
-               "ldr   %0,[%2]\n\t"
-               "cmp   %0,%4\n\t"
-               "bne   2f\n\t"
-               "swp   %1,%3,[%2]\n\t"
-               "cmp   %1,%0\n\t"
-               "swpne %0,%1,[%2]\n\t"
-               "bne   1b\n\t"
-               "2:"
-               : "=&r" (result), "=&r" (temp)
-               : "r" (p), "r" (newval), "r" (oldval)
-               : "cc", "memory"
-       );
-
-       return result;
-}
+typedef void (__kernel_dmb_t)(void);
+#define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
 
+namespace Atomic_md {
 
 /**
- * An atomic compare and swap for 64-bit integer values.
+ * An atomic compare and swap for 32-bit integer values.
  *
  * @param p      Pointer to memory address.
  * @param oldval Old value to be expected.
@@ -76,14 +49,14 @@ inline uint32_t Atomic::compare_and_swap(volatile uint32_t *p, uint32_t oldval,
  *
  * @return value of the memory location before the store
  */
-inline uint64_t Atomic::compare_and_swap(volatile uint64_t *p, uint64_t oldval, uint64_t newval)
+inline uint32_t compare_and_swap(volatile uint32_t *p, uint32_t oldval, uint32_t newval)
 {
-       return generic_compare_and_swap(p, oldval, newval);
+       return __sync_val_compare_and_swap(p, oldval, newval);
 }
 
 
 /**
- * An atomic compare and swap for pointer values.
+ * An atomic compare and swap for 64-bit integer values.
  *
  * @param p      Pointer to memory address.
  * @param oldval Old value to be expected.
@@ -91,38 +64,40 @@ inline uint64_t Atomic::compare_and_swap(volatile uint64_t *p, uint64_t oldval,
  *
  * @return value of the memory location before the store
  */
-inline void* Atomic::compare_and_swap(volatile void** p, void* oldval, void* newval)
+inline uint64_t compare_and_swap(volatile uint64_t *p, uint64_t oldval, uint64_t newval)
 {
-       return (void*) compare_and_swap((volatile uint32_t*) p, (uint32_t) oldval, (uint32_t) newval);
+       return Atomic::generic_compare_and_swap(p, oldval, newval);
 }
 
 
 /**
  * A memory barrier.
  */
-inline void Atomic::memory_barrier(void)
+inline void memory_barrier(void)
 {
-       __asm__ __volatile__ ("" : : : "memory");
+       __kernel_dmb();
 }
 
 
 /**
  * A write memory barrier.
  */
-inline void Atomic::write_memory_barrier(void)
+inline void write_memory_barrier(void)
 {
-       __asm__ __volatile__ ("" : : : "memory");
+       __kernel_dmb();
 }
 
 
 /**
  * An instruction barrier.
  */
-inline void Atomic::instruction_barrier(void)
+inline void instruction_barrier(void)
 {
        __asm__ __volatile__ ("" : : : "memory");
 }
 
+}
+
 #endif // _MD_ATOMIC_HPP