/* src/vm/jit/alpha/arch.h - architecture defines for Alpha
- Copyright (C) 1996-2005 R. Grafl, A. Krall, C. Kruegel, C. Oates,
- R. Obermaisser, M. Platter, M. Probst, S. Ring, E. Steiner,
- C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich, J. Wenninger,
- Institut f. Computersprachen - TU Wien
+ Copyright (C) 1996-2010
+ CACAOVM - Verein zur Foerderung der freien virtuellen Maschine CACAO
This file is part of CACAO.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
- 02111-1307, USA.
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA.
- Contact: cacao@complang.tuwien.ac.at
+*/
- Authors: Christian Thalinger
- Changes:
+#ifndef _ARCH_H
+#define _ARCH_H
- $Id: arch.h 2357 2005-04-22 17:37:57Z christian $
+#define JIT_COMPILER_VIA_SIGNAL
-*/
+#include "config.h"
-#ifndef _ARCH_H
-#define _ARCH_H
+/* define architecture features ***********************************************/
+#define SUPPORT_DIVISION 0
+#define SUPPORT_LONG 1
-/* preallocated registers *****************************************************/
+#define SUPPORT_I2F 1
+#define SUPPORT_I2D 1
+#define SUPPORT_L2F 1
+#define SUPPORT_L2D 1
-/* integer registers */
-
-#define REG_RESULT 0 /* to deliver method results */
+#define SUPPORT_F2I 0
+#define SUPPORT_F2L 0
+#define SUPPORT_D2I 0
+#define SUPPORT_D2L 0
-#define REG_RA 26 /* return address */
-#define REG_PV 27 /* procedure vector, must be provided by caller */
-#define REG_METHODPTR 28 /* pointer to the place from where the procedure */
- /* vector has been fetched */
-#define REG_ITMP1 25 /* temporary register */
-#define REG_ITMP2 28 /* temporary register and method pointer */
-#define REG_ITMP3 29 /* temporary register */
+#define SUPPORT_LONG_ADD 1
+#define SUPPORT_LONG_CMP 1
+#define SUPPORT_LONG_CMP_CONST 1
+#define SUPPORT_LONG_LOGICAL 1
+#define SUPPORT_LONG_SHIFT 1
+#define SUPPORT_LONG_MUL 1
+#define SUPPORT_LONG_DIV 0
-#define REG_ITMP1_XPTR 25 /* exception pointer = temporary register 1 */
-#define REG_ITMP2_XPC 28 /* exception pc = temporary register 2 */
+#define SUPPORT_LONG_DIV_POW2 1
+#define SUPPORT_LONG_REM_POW2 1
-#define REG_SP 30 /* stack pointer */
-#define REG_ZERO 31 /* always zero */
+#define SUPPORT_CONST_LOGICAL 1 /* AND, OR, XOR with immediates */
+#define SUPPORT_CONST_MUL 1 /* mutiply with immediate */
-/* floating point registers */
+#define SUPPORT_CONST_STORE 1 /* do we support const stores */
+#define SUPPORT_CONST_STORE_ZERO_ONLY 1 /* on some risc machines we can */
+ /* only store REG_ZERO */
-#define REG_FRESULT 0 /* to deliver floating point method results */
-#define REG_FTMP1 28 /* temporary floating point register */
-#define REG_FTMP2 29 /* temporary floating point register */
-#define REG_FTMP3 30 /* temporary floating point register */
+/* float **********************************************************************/
-#define REG_IFTMP 28 /* temporary integer and floating point register */
+#define SUPPORT_FLOAT 1
+#if defined(ENABLE_SOFT_FLOAT_CMP)
+# define SUPPORT_FLOAT_CMP 0
+#else
+# define SUPPORT_FLOAT_CMP 1
+#endif
-#define INT_SAV_CNT 7 /* number of int callee saved registers */
-#define INT_ARG_CNT 6 /* number of int argument registers */
-#define FLT_SAV_CNT 8 /* number of flt callee saved registers */
-#define FLT_ARG_CNT 6 /* number of flt argument registers */
+/* double *********************************************************************/
+#define SUPPORT_DOUBLE 1
-#define TRACE_ARGS_NUM 6
+#if defined(ENABLE_SOFT_FLOAT_CMP)
+# define SUPPORT_DOUBLE_CMP 0
+#else
+# define SUPPORT_DOUBLE_CMP 1
+#endif
-/* define architecture features ***********************************************/
+/* branches *******************************************************************/
-#define POINTERSIZE 8
-#define WORDS_BIGENDIAN 0
+#define SUPPORT_BRANCH_CONDITIONAL_CONDITION_REGISTER 0
+#define SUPPORT_BRANCH_CONDITIONAL_ONE_INTEGER_REGISTER 1
+#define SUPPORT_BRANCH_CONDITIONAL_TWO_INTEGER_REGISTERS 0
-#define U8_AVAILABLE 1
-#define USE_CODEMMAP 1
+/* exceptions *****************************************************************/
-/* #define USEBUILTINTABLE */
+#define SUPPORT_HARDWARE_DIVIDE_BY_ZERO 0
-#define SUPPORT_DIVISION 0
-#define SUPPORT_LONG 1
-#define SUPPORT_FLOAT 1
-#define SUPPORT_DOUBLE 1
-/* #define SUPPORT_IFCVT 1 */
-/* #define SUPPORT_FICVT 1 */
+/* stackframe *****************************************************************/
-#define SUPPORT_LONG_ADD 1
-#define SUPPORT_LONG_CMP 1
-#define SUPPORT_LONG_LOGICAL 1
-#define SUPPORT_LONG_SHIFT 1
-#define SUPPORT_LONG_MUL 1
-#define SUPPORT_LONG_DIV 0
-#define SUPPORT_LONG_ICVT 1
-#define SUPPORT_LONG_FCVT 1
+#define STACKFRMAE_RA_BETWEEN_FRAMES 0
+#define STACKFRAME_RA_TOP_OF_FRAME 1
+#define STACKFRAME_RA_LINKAGE_AREA 0
+#define STACKFRAME_LEAFMETHODS_RA_REGISTER 1
+#define STACKFRAME_SYNC_NEEDS_TWO_SLOTS 0
-#define SUPPORT_CONST_LOGICAL 1 /* AND, OR, XOR with immediates */
-#define SUPPORT_CONST_MUL 1 /* mutiply with immediate */
-#define SUPPORT_CONST_STORE 1 /* do we support const stores */
-#define SUPPORT_CONST_STORE_ZERO_ONLY 1 /* on some risc machines we can */
- /* only store REG_ZERO */
+/* replacement ****************************************************************/
+
+#define REPLACEMENT_PATCH_SIZE 4 /* bytes */
-#define CONDITIONAL_LOADCONST 1
+/* subtype ********************************************************************/
-/* #define CONSECUTIVE_INTEGER_ARGS */
-/* #define CONSECUTIVE_FLOAT_ARGS */
+#define USES_NEW_SUBTYPE 1
#endif /* _ARCH_H */
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