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Remove superfluous Super I/O res0/res1 lines.
[coreboot.git]
/
src
/
superio
/
winbond
/
w83627uhg
/
drwxr-xr-x
..
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866
Makefile.inc
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1139
chip.h
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4953
superio.c
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1593
w83627uhg.h
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1607
w83627uhg_early_serial.c
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projects / coreboot.git / tree