From e5508a728f2009024afe041c47ea1efc43526c96 Mon Sep 17 00:00:00 2001 From: ajordan Date: Mon, 16 Oct 2006 00:05:25 +0000 Subject: [PATCH] * src/vm/jit/sparc64/codegen.c: Ported to unified variables. * src/vm/jit/sparc64/emit.c: Likewise. * src/vm/jit/sparc64/md.c: Implemented md_codegen_get_pv_from_pc. * src/vm/jit/sparc64/codegen.h: Some fixes. * src/vm/jit/sparc64/asmpart.S: Likewise. --- src/vm/jit/sparc64/asmpart.S | 16 +- src/vm/jit/sparc64/codegen.c | 318 ++++++++--------------------------- src/vm/jit/sparc64/codegen.h | 68 +++++--- src/vm/jit/sparc64/emit.c | 31 ++-- src/vm/jit/sparc64/md.c | 23 ++- 5 files changed, 157 insertions(+), 299 deletions(-) diff --git a/src/vm/jit/sparc64/asmpart.S b/src/vm/jit/sparc64/asmpart.S index fcae9bb52..71c71cdaf 100644 --- a/src/vm/jit/sparc64/asmpart.S +++ b/src/vm/jit/sparc64/asmpart.S @@ -142,17 +142,18 @@ calljava_copyloop: calljava_nocopy: - mov %i0,itmp1 /* pass method pointer via itmp1 */ + mov %i0,itmp1 /* pass method pointer via itmp1 */ - setx asm_call_jit_compiler,%l0,mptr_itmp2 /* fake virtual function call (2 instr) */ - stx mptr_itmp2,[%sp + 17*8] /* store function address */ - addx %sp,16*8,mptr_itmp2 /* set method pointer */ + setx asm_call_jit_compiler,%l0,mptr_itmp2 /* fake virtual function call (2 instr) */ + stx mptr_itmp2,[%sp + 2047 + 17*8] /* store function address */ + add %sp,2047 + 16*8,mptr_itmp2 /* set method pointer */ - ldx [1*8 + mptr_itmp2], pv_caller /* method call as in Java */ + ldx [1*8 + mptr_itmp2], pv_caller /* method call as in Java */ jmpl pv_caller,ra_caller /* call JIT compiler */ nop calljava_jit2: - /* no need to restore pv */ + /* pretend to restore pv */ + add ra_caller,(asm_vm_call_method - calljava_jit2 + 8),pv_callee calljava_return: mov %o0, %i0 /* pass on the return value */ @@ -196,9 +197,10 @@ asm_call_jit_compiler: mov itmp1,%o0 /* pass methodinfo pointer */ mov mptr_itmp2,%o1 /* pass method pointer */ mov %fp,%o2 /* pass java sp (==fp) */ - mov ra_callee,%o3 /* pass Java ra */ + mov ra_caller,%o3 /* pass Java ra */ mov %o3,%o4 /* xpc is equal to ra */ call jit_asm_compile /* call jit compiler */ + nop mov %o0,pv_callee /* save return value into callee(!) pv */ /* the in's we have are also the in's of the*/ diff --git a/src/vm/jit/sparc64/codegen.c b/src/vm/jit/sparc64/codegen.c index d80803f96..e8e5590c5 100644 --- a/src/vm/jit/sparc64/codegen.c +++ b/src/vm/jit/sparc64/codegen.c @@ -94,8 +94,6 @@ bool codegen(jitdata *jd) codegendata *cd; registerdata *rd; s4 len, s1, s2, s3, d, disp; - s4 stackframesize; - stackptr src; varinfo *var; basicblock *bptr; instruction *iptr; @@ -107,6 +105,7 @@ bool codegen(jitdata *jd) methoddesc *md; rplpoint *replacementpoint; s4 fieldtype; + s4 varindex; /* get required compiler data */ @@ -137,17 +136,17 @@ bool codegen(jitdata *jd) savedregs_num += (INT_SAV_CNT - rd->savintreguse); savedregs_num += (FLT_SAV_CNT - rd->savfltreguse); - stackframesize = rd->memuse + savedregs_num; + cd->stackframesize = rd->memuse + savedregs_num; #if defined(ENABLE_THREADS) /* space to save argument of monitor_enter */ if (checksync && (m->flags & ACC_SYNCHRONIZED)) - stackframesize++; + cd->stackframesize++; #endif /* create method header */ (void) dseg_addaddress(cd, code); /* CodeinfoPointer */ - (void) dseg_adds4(cd, stackframesize * 8); /* FrameSize */ + (void) dseg_adds4(cd, cd->stackframesize * 8); /* FrameSize */ #if defined(ENABLE_THREADS) /* IsSync contains the offset relative to the stack pointer for the @@ -181,12 +180,12 @@ bool codegen(jitdata *jd) /* save register window and create stack frame (if necessary) */ - if (stackframesize) - M_SAVE(REG_SP, -stackframesize * 8, REG_SP); + if (cd->stackframesize) + M_SAVE(REG_SP, -cd->stackframesize * 8, REG_SP); /* save return address and used callee saved registers */ - p = stackframesize; + p = cd->stackframesize; for (i = FLT_SAV_CNT - 1; i >= rd->savfltreguse; i--) { p--; M_DST(rd->savfltregs[i], REG_SP, (WINSAVE_REGS + p) * 8); } @@ -197,29 +196,35 @@ bool codegen(jitdata *jd) for (p = 0, l = 0; p < md->paramcount; p++) { t = md->paramtypes[p].type; - var = &(rd->locals[l][t]); + + varindex = jd->local_map[l * 5 + t]; + l++; if (IS_2_WORD_TYPE(t)) /* increment local counter for 2 word types */ l++; - if (var->type < 0) + + if (varindex == UNUSED) continue; + + var = VAR(varindex); + s1 = md->params[p].regoff; if (IS_INT_LNG_TYPE(t)) { /* integer args */ if (!md->params[p].inmemory) { /* register arguments */ s2 = rd->argintregs[s1]; if (!(var->flags & INMEMORY)) { /* reg arg -> register */ - M_INTMOVE(s2, var->regoff); + M_INTMOVE(s2, var->vv.regoff); } else { /* reg arg -> spilled */ - M_STX(s2, REG_SP, (WINSAVE_REGS + var->regoff) * 8); + M_STX(s2, REG_SP, (WINSAVE_REGS + var->vv.regoff) * 8); } } else { /* stack arguments */ if (!(var->flags & INMEMORY)) { /* stack arg -> register */ - M_LDX(var->regoff, REG_SP, (stackframesize + s1) * 8); + M_LDX(var->vv.regoff, REG_SP, (cd->stackframesize + s1) * 8); } else { /* stack arg -> spilled */ - var->regoff = stackframesize + s1; + var->vv.regoff = cd->stackframesize + s1; } } @@ -227,18 +232,18 @@ bool codegen(jitdata *jd) if (!md->params[p].inmemory) { /* register arguments */ s2 = rd->argfltregs[s1]; if (!(var->flags & INMEMORY)) { /* reg arg -> register */ - M_FLTMOVE(s2, var->regoff); + M_FLTMOVE(s2, var->vv.regoff); } else { /* reg arg -> spilled */ - M_DST(s2, REG_SP, (WINSAVE_REGS + var->regoff) * 8); + M_DST(s2, REG_SP, (WINSAVE_REGS + var->vv.regoff) * 8); } } else { /* stack arguments */ if (!(var->flags & INMEMORY)) { /* stack-arg -> register */ - M_DLD(var->regoff, REG_SP, (stackframesize + s1) * 8); + M_DLD(var->vv.regoff, REG_SP, (cd->stackframesize + s1) * 8); } else { /* stack-arg -> spilled */ - var->regoff = stackframesize + s1; + var->vv.regoff = cd->stackframesize + s1; } } } @@ -281,64 +286,41 @@ bool codegen(jitdata *jd) /* copy interface registers to their destination */ - src = bptr->instack; len = bptr->indepth; MCODECHECK(64+len); #if defined(ENABLE_LSRA) if (opt_lsra) { - while (src != NULL) { + while (len) { len--; - if ((len == 0) && (bptr->type != BBTYPE_STD)) { + src = bptr->invars[len]; + if ((len == bptr->indepth-1) && (bptr->type == BBTYPE_EXH)) { /* d = reg_of_var(m, src, REG_ITMP1); */ if (!(src->flags & INMEMORY)) - d = src->regoff; + d = src->vv.regoff; else d = REG_ITMP1; M_INTMOVE(REG_ITMP1, d); emit_store(jd, NULL, src, d); } - src = src->prev; } } else { #endif - while (src != NULL) { + while (len) { len--; - if ((len == 0) && (bptr->type != BBTYPE_STD)) { - d = codegen_reg_of_var(rd, 0, src, REG_ITMP1); + var = VAR(bptr->invars[len]); + if ((len == bptr->indepth-1) && (bptr->type == BBTYPE_EXH)) { + d = codegen_reg_of_var(0, var, REG_ITMP1); M_INTMOVE(REG_ITMP1, d); - emit_store(jd, NULL, src, d); - - } else { - d = codegen_reg_of_var(rd, 0, src, REG_IFTMP); - if ((src->varkind != STACKVAR)) { - s2 = src->type; - if (IS_FLT_DBL_TYPE(s2)) { - if (!(rd->interfaces[len][s2].flags & INMEMORY)) { - s1 = rd->interfaces[len][s2].regoff; - M_DBLMOVE(s1, d); - } else { - M_DLD(d, REG_SP, rd->interfaces[len][s2].regoff * 8); - } - emit_store(jd, NULL, src, d); - - } else { - if (!(rd->interfaces[len][s2].flags & INMEMORY)) { - s1 = rd->interfaces[len][s2].regoff; - M_INTMOVE(s1, d); - } else { - M_LDX(d, REG_SP, rd->interfaces[len][s2].regoff * 8); + emit_store(jd, NULL, var, d); } - emit_store(jd, NULL, src, d); + else { + assert((var->flags & INOUT)); } } - } - src = src->prev; - } #if defined(ENABLE_LSRA) } #endif - /* walk through all instructions */ len = bptr->icount; @@ -420,73 +402,22 @@ bool codegen(jitdata *jd) break; - /* load/store operations **********************************************/ + /* load/store/copy/move operations ************************************/ case ICMD_ILOAD: /* ... ==> ..., content of local variable */ - case ICMD_LLOAD: /* op1 = local variable */ - case ICMD_ALOAD: - - d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); - if ((iptr->dst.var->varkind == LOCALVAR) && - (iptr->dst.var->varnum == iptr->s1.localindex)) - break; - var = &(rd->locals[iptr->s1.localindex][iptr->opc - ICMD_ILOAD]); - if (var->flags & INMEMORY) { - M_ALD(REG_SP, var->regoff * 8, d); - } else { - M_INTMOVE(var->regoff, d); - } - emit_store_dst(jd, iptr, d); - break; - + case ICMD_LLOAD: /* ... ==> ..., content of local variable */ + case ICMD_ALOAD: /* ... ==> ..., content of local variable */ case ICMD_FLOAD: /* ... ==> ..., content of local variable */ - case ICMD_DLOAD: /* op1 = local variable */ - - d = codegen_reg_of_dst(jd, iptr, REG_FTMP1); - if ((iptr->dst.var->varkind == LOCALVAR) && - (iptr->dst.var->varnum == iptr->s1.localindex)) - break; - var = &(rd->locals[iptr->s1.localindex][iptr->opc - ICMD_ILOAD]); - if (var->flags & INMEMORY) { - M_DLD(d, REG_SP, var->regoff * 8); - } else { - M_FLTMOVE(var->regoff, d); - } - emit_store_dst(jd, iptr, d); - break; - - + case ICMD_DLOAD: /* ... ==> ..., content of local variable */ case ICMD_ISTORE: /* ..., value ==> ... */ - case ICMD_LSTORE: /* op1 = local variable */ - case ICMD_ASTORE: - - if ((iptr->s1.var->varkind == LOCALVAR) && - (iptr->s1.var->varnum == iptr->dst.localindex)) - break; - var = &(rd->locals[iptr->dst.localindex][iptr->opc - ICMD_ISTORE]); - if (var->flags & INMEMORY) { - s1 = emit_load_s1(jd, iptr, REG_ITMP1); - M_STX(s1, REG_SP, var->regoff * 8); - } else { - s1 = emit_load_s1(jd, iptr, var->regoff); - M_INTMOVE(s1, var->regoff); - } - break; - + case ICMD_LSTORE: /* ..., value ==> ... */ + case ICMD_ASTORE: /* ..., value ==> ... */ case ICMD_FSTORE: /* ..., value ==> ... */ - case ICMD_DSTORE: /* op1 = local variable */ + case ICMD_DSTORE: /* ..., value ==> ... */ + case ICMD_COPY: + case ICMD_MOVE: - if ((iptr->s1.var->varkind == LOCALVAR) && - (iptr->s1.var->varnum == iptr->dst.localindex)) - break; - var = &(rd->locals[iptr->dst.localindex][iptr->opc - ICMD_ISTORE]); - if (var->flags & INMEMORY) { - s1 = emit_load_s1(jd, iptr, REG_FTMP1); - M_DST(s1, REG_SP, var->regoff * 8); - } else { - s1 = emit_load_s1(jd, iptr, var->regoff); - M_FLTMOVE(s1, var->regoff); - } + emit_copy(jd, iptr, VAROP(iptr->s1), VAROP(iptr->dst)); break; @@ -498,57 +429,6 @@ bool codegen(jitdata *jd) case ICMD_POP2: /* ..., value, value ==> ... */ break; - case ICMD_DUP: /* ..., a ==> ..., a, a */ - - M_COPY(iptr->s1.var, iptr->dst.var); - break; - - case ICMD_DUP_X1: /* ..., a, b ==> ..., b, a, b */ - - M_COPY(iptr->dst.dupslots[ 1], iptr->dst.dupslots[2+2]); - M_COPY(iptr->dst.dupslots[ 0], iptr->dst.dupslots[2+1]); - M_COPY(iptr->dst.dupslots[2+2], iptr->dst.dupslots[2+0]); - break; - - case ICMD_DUP_X2: /* ..., a, b, c ==> ..., c, a, b, c */ - - M_COPY(iptr->dst.dupslots[ 2], iptr->dst.dupslots[3+3]); - M_COPY(iptr->dst.dupslots[ 1], iptr->dst.dupslots[3+2]); - M_COPY(iptr->dst.dupslots[ 0], iptr->dst.dupslots[3+1]); - M_COPY(iptr->dst.dupslots[3+3], iptr->dst.dupslots[3+0]); - break; - - case ICMD_DUP2: /* ..., a, b ==> ..., a, b, a, b */ - - M_COPY(iptr->dst.dupslots[ 1], iptr->dst.dupslots[2+1]); - M_COPY(iptr->dst.dupslots[ 0], iptr->dst.dupslots[2+0]); - break; - - case ICMD_DUP2_X1: /* ..., a, b, c ==> ..., b, c, a, b, c */ - - M_COPY(iptr->dst.dupslots[ 2], iptr->dst.dupslots[3+4]); - M_COPY(iptr->dst.dupslots[ 1], iptr->dst.dupslots[3+3]); - M_COPY(iptr->dst.dupslots[ 0], iptr->dst.dupslots[3+2]); - M_COPY(iptr->dst.dupslots[3+4], iptr->dst.dupslots[3+1]); - M_COPY(iptr->dst.dupslots[3+3], iptr->dst.dupslots[3+0]); - break; - - case ICMD_DUP2_X2: /* ..., a, b, c, d ==> ..., c, d, a, b, c, d */ - - M_COPY(iptr->dst.dupslots[ 3], iptr->dst.dupslots[4+5]); - M_COPY(iptr->dst.dupslots[ 2], iptr->dst.dupslots[4+4]); - M_COPY(iptr->dst.dupslots[ 1], iptr->dst.dupslots[4+3]); - M_COPY(iptr->dst.dupslots[ 0], iptr->dst.dupslots[4+2]); - M_COPY(iptr->dst.dupslots[4+5], iptr->dst.dupslots[4+1]); - M_COPY(iptr->dst.dupslots[4+4], iptr->dst.dupslots[4+0]); - break; - - case ICMD_SWAP: /* ..., a, b ==> ..., b, a */ - - M_COPY(iptr->dst.dupslots[ 1], iptr->dst.dupslots[2+0]); - M_COPY(iptr->dst.dupslots[ 0], iptr->dst.dupslots[2+1]); - break; - /* integer operations *************************************************/ @@ -606,6 +486,7 @@ bool codegen(jitdata *jd) emit_store_dst(jd, iptr, d); break; + case ICMD_IINC: case ICMD_IADDCONST: /* ..., value ==> ..., value + constant */ /* sx.val.i = constant */ @@ -1044,26 +925,6 @@ bool codegen(jitdata *jd) break; - case ICMD_IINC: /* ..., value ==> ..., value + constant */ - /* s1.localindex = variable, sx.val.i = constant */ - - var = &(rd->locals[iptr->s1.localindex][TYPE_INT]); - if (var->flags & INMEMORY) { - s1 = REG_ITMP1; - M_LDX(s1, REG_SP, var->regoff * 8); - } else - s1 = var->regoff; - if ((iptr->sx.val.i >= -4096) && (iptr->sx.val.i <= 4095)) { - M_ADD_IMM(s1, iptr->sx.val.i, s1); - } else { - ICONST(REG_ITMP2, iptr->sx.val.i); - M_ADD(s1, REG_ITMP2, s1); - } - if (var->flags & INMEMORY) - M_STX(s1, REG_SP, var->regoff * 8); - break; - - /* floating operations ************************************************/ case ICMD_FNEG: /* ..., value ==> ..., - value */ @@ -1941,6 +1802,8 @@ bool codegen(jitdata *jd) break; case ICMD_GOTO: /* ... ==> ... */ + case ICMD_RET: /* ... ==> ... */ + M_BR(0); codegen_addreference(cd, iptr->dst.block); M_NOP; @@ -1949,20 +1812,8 @@ bool codegen(jitdata *jd) case ICMD_JSR: /* ... ==> ... */ - dseg_addtarget(cd, iptr->sx.s23.s3.jsrtarget.block); - M_ALD(REG_ITMP1, REG_PV, -(cd->dseglen)); - M_JMP(REG_ITMP1, REG_ITMP1, REG_ZERO); /* REG_ITMP1 = return address */ - M_NOP; - break; - - case ICMD_RET: /* ... ==> ... */ - /* s1.localindex = local variable */ - var = &(rd->locals[iptr->s1.localindex][TYPE_ADR]); - if (var->flags & INMEMORY) { - M_ALD(REG_ITMP1, REG_SP, var->regoff * 8); - M_RET(REG_ITMP1); - } else - M_RET(var->regoff); + M_BR(0); + codegen_addreference(cd, iptr->sx.s23.s3.jsrtarget.block); M_NOP; ALIGNCODENOP; break; @@ -2375,9 +2226,7 @@ nowperformreturn: { s4 i, p; - p = stackframesize; - - /* call trace function */ + p = cd->stackframesize; #if !defined(NDEBUG) if (opt_verbosecall) { @@ -2557,31 +2406,35 @@ gen_method: /* copy arguments to registers or stack location */ - for (s3 = s3 - 1; s3 >= 0; s3--, src = src->prev) { - if (src->varkind == ARGVAR) + for (s3 = s3 - 1; s3 >= 0; s3--) { + var = VAR(iptr->sx.s23.s2.args[s3]); + + if (var->flags & PREALLOC) continue; - if (IS_INT_LNG_TYPE(src->type)) { + + if (IS_INT_LNG_TYPE(var->type)) { if (!md->params[s3].inmemory) { s1 = rd->argintregs[md->params[s3].regoff]; - d = emit_load_s1(jd, iptr, s1); + d = emit_load(jd, iptr, var, s1); M_INTMOVE(d, s1); - } else { - d = emit_load_s1(jd, iptr, REG_ITMP1); + } + else { + d = emit_load(jd, iptr, var, REG_ITMP1); M_STX(d, REG_SP, md->params[s3].regoff * 8); } - - } else { + } + else { if (!md->params[s3].inmemory) { s1 = rd->argfltregs[md->params[s3].regoff]; - d = emit_load_s1(jd, iptr, s1); - if (IS_2_WORD_TYPE(src->type)) + d = emit_load(jd, iptr, var, s1); + if (IS_2_WORD_TYPE(var->type)) M_DMOV(d, s1); else M_FMOV(d, s1); - - } else { - d = emit_load_s1(jd, iptr, REG_FTMP1); - if (IS_2_WORD_TYPE(src->type)) + } + else { + d = emit_load(jd, iptr, var, REG_FTMP1); + if (IS_2_WORD_TYPE(var->type)) M_DST(d, REG_SP, md->params[s3].regoff * 8); else M_FST(d, REG_SP, md->params[s3].regoff * 8); @@ -2921,45 +2774,14 @@ gen_method: } /* for instruction */ - /* copy values to interface registers */ - src = bptr->outstack; - len = bptr->outdepth; - MCODECHECK(64+len); -#if defined(ENABLE_LSRA) - if (!opt_lsra) -#endif - while (src) { - len--; - if ((src->varkind != STACKVAR)) { - s2 = src->type; - if (IS_FLT_DBL_TYPE(s2)) { - s1 = emit_load(jd, NULL, src, REG_FTMP1); - if (!(rd->interfaces[len][s2].flags & INMEMORY)) { - M_FLTMOVE(s1,rd->interfaces[len][s2].regoff); - } - else { - M_DST(s1, REG_SP, 8 * rd->interfaces[len][s2].regoff); - } - } - else { - s1 = emit_load(jd, NULL, src, REG_ITMP1); - if (!(rd->interfaces[len][s2].flags & INMEMORY)) { - M_INTMOVE(s1,rd->interfaces[len][s2].regoff); - } - else { - M_STX(s1, REG_SP, 8 * rd->interfaces[len][s2].regoff); - } - } - } - src = src->prev; - } + } /* if (bptr -> flags >= BBREACHED) */ } /* for basic block */ dseg_createlinenumbertable(cd); - /* generate stubs */ + /* generate exception and patcher stubs */ emit_exception_stubs(jd); emit_patcher_stubs(jd); diff --git a/src/vm/jit/sparc64/codegen.h b/src/vm/jit/sparc64/codegen.h index 1549e6949..86477ef46 100644 --- a/src/vm/jit/sparc64/codegen.h +++ b/src/vm/jit/sparc64/codegen.h @@ -129,21 +129,25 @@ * imm ..... switch to use rs2 as constant 13bit integer * (REG means: use b as register number) * (IMM means: use b as signed immediate value) - * */ - + */ #define M_OP3(op,op3,rd,rs1,rs2,imm) \ - *((u4 *) cd->mcodeptr++) = ((((s4) (op)) << 30) | ((rd) << 25) | ((op3) << 19) | ((rs1) << 14) | ((imm)<<13) | (imm?((rs2)&0x1fff):(rs2)) ) + do { \ + *((u4 *) cd->mcodeptr) = ((((s4) (op)) << 30) | ((rd) << 25) | ((op3) << 19) | ((rs1) << 14) | ((imm)<<13) | (imm?((rs2)&0x1fff):(rs2)) ); \ + cd->mcodeptr += 4; \ + } while (0) + /* 3-address-operations: M_OP3C * rcond ... condition opcode * rs2 ..... register number or 10bit signed immediate * */ - #define M_OP3C(op,op3,rcond,rd,rs1,rs2,imm) \ - *((u4 *) cd->mcodeptr++) = ((((s4) (op)) << 30) | ((rd) << 25) | ((op3) << 19) | ((rs1) << 14) | ((imm)<<13) | \ - ((rcond) << 10) | (imm?((rs2)&0x3ff):(rs2)) ) - + do { \ + *((u4 *) cd->mcodeptr) = ((((s4) (op)) << 30) | ((rd) << 25) | ((op3) << 19) | ((rs1) << 14) | ((imm)<<13) | \ + ((rcond) << 10) | (imm?((rs2)&0x3ff):(rs2)) ); \ + cd->mcodeptr += 4; \ + } while (0) /* shift Format 3 @@ -156,8 +160,12 @@ * x ...... 0 => 32, 1 => 64 bit shift */ #define M_SHFT(op,op3,rs1,rs2,rd,imm,x) \ - *((u4 *) cd->mcodeptr++) = ( (((s4)(op)) << 30) | ((op3) << 19) | ((rd) << 25) | ((rs1) << 14) | ((rs2) << 0) | \ - ((imm) << 13) | ((x) << 12) ) + do { \ + *((u4 *) cd->mcodeptr) = ( (((s4)(op)) << 30) | ((op3) << 19) | ((rd) << 25) | ((rs1) << 14) | ((rs2) << 0) | \ + ((imm) << 13) | ((x) << 12) ); \ + cd->mcodeptr += 4; \ + } while (0) + /* Format 4 * op ..... opcode @@ -168,12 +176,12 @@ * imm .... switch for constant * cc{0-2} 32-bit 64-bit or fp condition */ - #define M_FMT4(op,op3,rd,rs2,cond,cc2,cc1,cc0,imm) \ - *((u4 *) cd->mcodeptr++) = ( (((s4)(op)) << 30) | ((op3) << 19) | ((rd) << 25) | ((cc2) << 18) | ((cond) << 14) | \ - ((imm) << 13) | ((cc1) << 12) | ((cc0) << 11) | ((rs2) << 0) ) - - + do { \ + *((u4 *) cd->mcodeptr) = ( (((s4)(op)) << 30) | ((op3) << 19) | ((rd) << 25) | ((cc2) << 18) | ((cond) << 14) | \ + ((imm) << 13) | ((cc1) << 12) | ((cc0) << 11) | ((rs2) << 0) ); \ + cd->mcodeptr += 4; \ + } while (0) /* 3-address-floating-point-operation @@ -185,7 +193,10 @@ !!! 6-bit to 5-bit conversion done here !!! */ #define M_FOP3(op,op3,opf,rd,rs1,rs2) \ - *((u4 *) cd->mcodeptr++) = ( (((s4)(op))<<30) | ((rd*2)<<25) | ((op3)<<19) | ((rs1*2) << 14) | ((opf)<<5) | (rs2*2) ) + do { \ + *((u4 *) cd->mcodeptr) = ( (((s4)(op))<<30) | ((rd*2)<<25) | ((op3)<<19) | ((rs1*2) << 14) | ((opf)<<5) | (rs2*2) ); \ + cd->mcodeptr += 4; \ + } while (0) /**** format 2 operations ********/ @@ -199,8 +210,12 @@ anul .... annullment bit */ #define M_BRAREG(op,rcond,rs1,disp16,p,anul) \ - *((u4 *) cd->mcodeptr++) = ( (((s4)(op))<<30) | ((anul)<<29) | (0<<28) | ((rcond)<<25) | (3<<22) | \ - ( ((disp16)& 0xC000) << 6 ) | (p << 19) | ((rs1) << 14) | ((disp16)&0x3fff) ) + do { \ + *((u4 *) cd->mcodeptr) = ( (((s4)(op))<<30) | ((anul)<<29) | (0<<28) | ((rcond)<<25) | (3<<22) | \ + ( ((disp16)& 0xC000) << 6 ) | (p << 19) | ((rs1) << 14) | ((disp16)&0x3fff) ); \ + cd->mcodeptr += 4; \ + } while (0) + /* branch on integer reg instruction op,op2 .... opcodes @@ -211,17 +226,24 @@ anul .... annullment bit */ #define M_BRACC(op,op2,cond,disp19,ccx,p,anul) \ - *((u4 *) cd->mcodeptr++) = ( (((s4)(op))<<30) | ((anul)<<29) | ((cond)<<25) | (op2<<22) | (ccx<<20) | \ - (p << 19 ) | (disp19) ) - -/************** end-user instructions (try to follow asm style) ***************/ + do { \ + *((u4 *) cd->mcodeptr) = ( (((s4)(op))<<30) | ((anul)<<29) | ((cond)<<25) | (op2<<22) | (ccx<<20) | \ + (p << 19 ) | (disp19) ); \ + cd->mcodeptr += 4; \ + } while (0) + +/************** end-user instructions (see a SPARC asm manual) ***************/ #define M_SETHI(imm22, rd) \ - *((u4 *) cd->mcodeptr++) = ((((s4)(0x00)) << 30) | ((rd) << 25) | ((0x04)<<22) | ((imm22)&0x3FFFFF) ) + do { \ + *((u4 *) cd->mcodeptr) = ((((s4)(0x00)) << 30) | ((rd) << 25) | ((0x04)<<22) | ((imm22)&0x3FFFFF) ); \ + cd->mcodeptr += 4; \ + } while (0) + -#define M_NOP (M_SETHI(0,0)) /* nop */ +#define M_NOP M_SETHI(0,0) /* nop */ #define M_AND(rs1,rs2,rd) M_OP3(0x02,0x01,rd,rs1,rs2,REG) /* 64b c = a & b */ #define M_AND_IMM(rs1,rs2,rd) M_OP3(0x02,0x01,rd,rs1,rs2,IMM) diff --git a/src/vm/jit/sparc64/emit.c b/src/vm/jit/sparc64/emit.c index d65aee7bd..98e8db12c 100644 --- a/src/vm/jit/sparc64/emit.c +++ b/src/vm/jit/sparc64/emit.c @@ -43,7 +43,6 @@ #include "vm/jit/sparc64/codegen.h" -/* code generation functions **************************************************/ /* emit_load ******************************************************************* @@ -51,9 +50,10 @@ *******************************************************************************/ -s4 emit_load(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg) +s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg) { codegendata *cd; + s4 disp; s4 reg; /* get required compiler data */ @@ -63,15 +63,17 @@ s4 emit_load(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg) if (src->flags & INMEMORY) { COUNT_SPILLS; + disp = src->vv.regoff * 8; + if (IS_FLT_DBL_TYPE(src->type)) - M_DLD(tempreg, REG_SP, src->regoff * 8); + M_DLD(tempreg, REG_SP, disp); else - M_LDX(tempreg, REG_SP, src->regoff * 8); + M_LDX(tempreg, REG_SP, disp); reg = tempreg; } else - reg = src->regoff; + reg = src->vv.regoff; return reg; } @@ -79,13 +81,14 @@ s4 emit_load(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg) /* emit_store ****************************************************************** - Emit a possible store for the given variable. + Emits a possible store to variable. *******************************************************************************/ -void emit_store(jitdata *jd, instruction *iptr, stackptr dst, s4 d) +void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d) { codegendata *cd; + s4 disp; /* get required compiler data */ @@ -94,10 +97,12 @@ void emit_store(jitdata *jd, instruction *iptr, stackptr dst, s4 d) if (dst->flags & INMEMORY) { COUNT_SPILLS; + disp = dst->vv.regoff * 8; + if (IS_FLT_DBL_TYPE(dst->type)) - M_DST(d, REG_SP, dst->regoff * 8); + M_DST(d, REG_SP, disp); else - M_STX(d, REG_SP, dst->regoff * 8); + M_STX(d, REG_SP, disp); } } @@ -108,7 +113,7 @@ void emit_store(jitdata *jd, instruction *iptr, stackptr dst, s4 d) *******************************************************************************/ -void emit_copy(jitdata *jd, instruction *iptr, stackptr src, stackptr dst) +void emit_copy(jitdata *jd, instruction *iptr, varinfo *src, varinfo *dst) { codegendata *cd; registerdata *rd; @@ -119,7 +124,7 @@ void emit_copy(jitdata *jd, instruction *iptr, stackptr src, stackptr dst) cd = jd->cd; rd = jd->rd; - if ((src->regoff != dst->regoff) || + if ((src->vv.regoff != dst->vv.regoff) || ((src->flags ^ dst->flags) & INMEMORY)) { /* If one of the variables resides in memory, we can eliminate @@ -127,12 +132,12 @@ void emit_copy(jitdata *jd, instruction *iptr, stackptr src, stackptr dst) order of getting the destination register and the load. */ if (IS_INMEMORY(src->flags)) { - d = codegen_reg_of_var(rd, iptr->opc, dst, REG_IFTMP); + d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP); s1 = emit_load(jd, iptr, src, d); } else { s1 = emit_load(jd, iptr, src, REG_IFTMP); - d = codegen_reg_of_var(rd, iptr->opc, dst, s1); + d = codegen_reg_of_var(iptr->opc, dst, s1); } if (s1 != d) { diff --git a/src/vm/jit/sparc64/md.c b/src/vm/jit/sparc64/md.c index fe971dcac..b32e9fa50 100644 --- a/src/vm/jit/sparc64/md.c +++ b/src/vm/jit/sparc64/md.c @@ -62,7 +62,8 @@ u1 *md_stacktrace_get_returnaddress(u1 *sp, u4 framesize) Machine code: - 6b5b4000 jsr (pv) + 6b5b4000 jmpl (pv) + 10000000 nop 277afffe ldah pv,-2(ra) 237ba61c lda pv,-23012(pv) @@ -71,18 +72,22 @@ u1 *md_stacktrace_get_returnaddress(u1 *sp, u4 framesize) u1 *md_codegen_get_pv_from_pc(u1 *ra) { u1 *pv; - u4 mcode; - s4 offset; + u8 mcode; + u4 mcode_masked; + s2 offset; pv = ra; - /* get first instruction word after jump */ - - mcode = *((u4 *) ra); + /* get the instruction word after jump and nop */ + mcode = *((u4 *) (ra+8) ); /* check if we have 2 instructions (ldah, lda) */ - if ((mcode >> 16) == 0x277a) { + /* shift instruction word, mask rd and rs1 */ + mcode_masked = (mcode >> 13) & 0x60fc1; + + if (mcode_masked == 0x40001) { +#if 0 /* get displacement of first instruction (ldah) */ offset = (s4) (mcode << 16); @@ -101,8 +106,10 @@ u1 *md_codegen_get_pv_from_pc(u1 *ra) /* get displacement of first instruction (lda) */ assert((mcode >> 16) == 0x237a); +#endif + /* mask and extend the negative sign for the 13 bit immediate */ + offset = (s2) ((mcode & 0x00001fff) | 0xffffe000); - offset = (s2) (mcode & 0x0000ffff); pv += offset; } -- 2.25.1