From c541e1bebde711975477f2314106d7b0799fccd7 Mon Sep 17 00:00:00 2001 From: Kevin O'Connor Date: Sat, 21 Jun 2008 12:24:14 -0400 Subject: [PATCH] Add code (currently disabled) to mask run away irqs. Add handler that can react to any unknown hardware irq by masking that irq. This can be useful for finding/fixing run away irq issues. Don't currently register these hardware irq handlers Also, sort and improve default debug levels for bios handlers. --- Makefile | 2 +- src/config.h | 25 ++++++++++++----------- src/pic.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++++ src/pic.h | 37 ++++++++++++++++----------------- src/post.c | 9 +++++++++ src/romlayout.S | 3 +++ 6 files changed, 99 insertions(+), 31 deletions(-) create mode 100644 src/pic.c diff --git a/Makefile b/Makefile index ca2a930..932cba5 100644 --- a/Makefile +++ b/Makefile @@ -9,7 +9,7 @@ OUT=out/ # Source files SRCBOTH=output.c util.c floppy.c ata.c system.c mouse.c kbd.c pci.c boot.c \ - serial.c clock.c + serial.c clock.c pic.c SRC16=$(SRCBOTH) disk.c cdrom.c apm.c pcibios.c SRC32=$(SRCBOTH) post.c shadow.c rombios32.c post_menu.c memmap.c coreboot.c \ acpi.c pirtable.c diff --git a/src/config.h b/src/config.h index 3f5782f..89ec8f1 100644 --- a/src/config.h +++ b/src/config.h @@ -72,27 +72,28 @@ // Debugging levels. If non-zero and CONFIG_DEBUG_LEVEL is greater // than the specified value, then the corresponding irq handler will // report every enter event. +#define DEBUG_ISR_nmi 1 #define DEBUG_HDL_05 1 -#define DEBUG_HDL_10 1 +#define DEBUG_ISR_08 20 +#define DEBUG_ISR_09 9 +#define DEBUG_ISR_0e 9 +#define DEBUG_HDL_10 20 #define DEBUG_HDL_11 1 #define DEBUG_HDL_12 1 +#define DEBUG_HDL_13 10 +#define DEBUG_HDL_14 1 #define DEBUG_HDL_15 9 -#define DEBUG_ISR_nmi 1 -#define DEBUG_ISR_75 1 #define DEBUG_HDL_16 9 -#define DEBUG_ISR_09 9 +#define DEBUG_HDL_17 1 #define DEBUG_HDL_18 1 #define DEBUG_HDL_19 1 #define DEBUG_HDL_1a 9 -#define DEBUG_ISR_1c 9 -#define DEBUG_ISR_08 9 -#define DEBUG_ISR_70 9 +#define DEBUG_ISR_1c 20 #define DEBUG_HDL_40 1 -#define DEBUG_HDL_13 9 -#define DEBUG_ISR_76 9 -#define DEBUG_HDL_14 1 -#define DEBUG_HDL_17 1 +#define DEBUG_ISR_70 9 #define DEBUG_ISR_74 9 -#define DEBUG_ISR_0e 9 +#define DEBUG_ISR_75 1 +#define DEBUG_ISR_76 10 +#define DEBUG_ISR_hwirq 30 #endif // config.h diff --git a/src/pic.c b/src/pic.c new file mode 100644 index 0000000..7088724 --- /dev/null +++ b/src/pic.c @@ -0,0 +1,54 @@ +// Helpers for working with i8259 interrupt controller. +// +// Copyright (C) 2008 Kevin O'Connor +// Copyright (C) 2002 MandrakeSoft S.A. +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "pic.h" + +void +pic_setup() +{ + dprintf(3, "init pic\n"); + // Send ICW1 (select OCW1 + will send ICW4) + outb(0x11, PORT_PIC1_CMD); + outb(0x11, PORT_PIC2_CMD); + // Send ICW2 (base irqs: 0x08-0x0f for irq0-7, 0x70-0x78 for irq8-15) + outb(0x08, PORT_PIC1_DATA); + outb(0x70, PORT_PIC2_DATA); + // Send ICW3 (cascaded pic ids) + outb(0x04, PORT_PIC1_DATA); + outb(0x02, PORT_PIC2_DATA); + // Send ICW4 (enable 8086 mode) + outb(0x01, PORT_PIC1_DATA); + outb(0x01, PORT_PIC2_DATA); + // Mask all irqs (except cascaded PIC2 irq) + outb(~PIC1_IRQ2, PORT_PIC1_DATA); + outb(~0, PORT_PIC2_DATA); +} + +// Handler for otherwise unused hardware irqs. +void VISIBLE16 +handle_hwirq(struct bregs *regs) +{ + debug_isr(DEBUG_ISR_hwirq); + + u8 isr1 = get_pic1_isr(); + if (! isr1) { + dprintf(1, "Got hwirq with no ISR\n"); + return; + } + + u8 isr2 = get_pic2_isr(); + u16 isr = isr2<<8 | isr1; + dprintf(1, "Masking noisy irq %x\n", isr); + if (isr2) { + mask_pic2(isr2); + eoi_pic2(); + } else { + if (! (isr1 & 0x2)) // don't ever mask the cascaded irq + mask_pic1(isr1); + eoi_pic1(); + } +} diff --git a/src/pic.h b/src/pic.h index dc151a2..8775191 100644 --- a/src/pic.h +++ b/src/pic.h @@ -49,6 +49,18 @@ unmask_pic2(u8 irq) outb(inb(PORT_PIC2_DATA) & ~irq, PORT_PIC2_DATA); } +static inline void +mask_pic1(u8 irq) +{ + outb(inb(PORT_PIC1_DATA) | irq, PORT_PIC1_DATA); +} + +static inline void +mask_pic2(u8 irq) +{ + outb(inb(PORT_PIC2_DATA) | irq, PORT_PIC2_DATA); +} + static inline u8 get_pic1_isr() { @@ -57,25 +69,14 @@ get_pic1_isr() return inb(PORT_PIC1_CMD); } -static inline void -pic_setup() +static inline u8 +get_pic2_isr() { - dprintf(3, "init pic\n"); - // Send ICW1 (select OCW1 + will send ICW4) - outb(0x11, PORT_PIC1_CMD); - outb(0x11, PORT_PIC2_CMD); - // Send ICW2 (base irqs: 0x08-0x0f for irq0-7, 0x70-0x78 for irq8-15) - outb(0x08, PORT_PIC1_DATA); - outb(0x70, PORT_PIC2_DATA); - // Send ICW3 (cascaded pic ids) - outb(0x04, PORT_PIC1_DATA); - outb(0x02, PORT_PIC2_DATA); - // Send ICW4 (enable 8086 mode) - outb(0x01, PORT_PIC1_DATA); - outb(0x01, PORT_PIC2_DATA); - // Mask all irqs (except cascaded PIC2 irq) - outb(~PIC1_IRQ2, PORT_PIC1_DATA); - outb(~0, PORT_PIC2_DATA); + // 0x0b == select OCW1 + read ISR + outb(0x0b, PORT_PIC2_CMD); + return inb(PORT_PIC2_CMD); } +void pic_setup(); + #endif // pic.h diff --git a/src/post.c b/src/post.c index 1b26e2b..33f14f4 100644 --- a/src/post.c +++ b/src/post.c @@ -36,7 +36,12 @@ init_bda() SET_BDA(ivecs[0x08].offset, OFFSET_entry_08); SET_BDA(ivecs[0x09].offset, OFFSET_entry_09); + //SET_BDA(ivecs[0x0a].offset, OFFSET_entry_hwirq); + //SET_BDA(ivecs[0x0b].offset, OFFSET_entry_hwirq); + //SET_BDA(ivecs[0x0c].offset, OFFSET_entry_hwirq); + //SET_BDA(ivecs[0x0d].offset, OFFSET_entry_hwirq); SET_BDA(ivecs[0x0e].offset, OFFSET_entry_0e); + //SET_BDA(ivecs[0x0f].offset, OFFSET_entry_hwirq); SET_BDA(ivecs[0x10].offset, OFFSET_entry_10); SET_BDA(ivecs[0x11].offset, OFFSET_entry_11); SET_BDA(ivecs[0x12].offset, OFFSET_entry_12); @@ -51,9 +56,13 @@ init_bda() SET_BDA(ivecs[0x1c].offset, OFFSET_entry_1c); SET_BDA(ivecs[0x40].offset, OFFSET_entry_40); SET_BDA(ivecs[0x70].offset, OFFSET_entry_70); + //SET_BDA(ivecs[0x71].offset, OFFSET_entry_hwirq); + //SET_BDA(ivecs[0x72].offset, OFFSET_entry_hwirq); + //SET_BDA(ivecs[0x73].offset, OFFSET_entry_hwirq); SET_BDA(ivecs[0x74].offset, OFFSET_entry_74); SET_BDA(ivecs[0x75].offset, OFFSET_entry_75); SET_BDA(ivecs[0x76].offset, OFFSET_entry_76); + //SET_BDA(ivecs[0x77].offset, OFFSET_entry_hwirq); // set vector 0x79 to zero // this is used by 'gardian angel' protection system diff --git a/src/romlayout.S b/src/romlayout.S index c852261..daa8d7a 100644 --- a/src/romlayout.S +++ b/src/romlayout.S @@ -446,6 +446,9 @@ entry_18: ORG 0xe82e IRQ_ENTRY_ARG 16 +entry_hwirq: + ENTRY handle_hwirq + ORG 0xe987 IRQ_ENTRY 09 -- 2.25.1