From 9a8609f862b89efbb52106a94ad51f55bb67e05a Mon Sep 17 00:00:00 2001
From: Kevin O'Connor <kevin@koconnor.net>
Date: Fri, 1 Jan 2010 12:50:04 -0500
Subject: [PATCH] Make MTRR region 0xc0000-0x100000 be cached.

Use the "write protect" setting instead of "uncached" for that region.
Also, make sure to clear all variable MTRRs before enabling them.
---
 src/mtrr.c | 54 +++++++++++++++++++++++++++++-------------------------
 1 file changed, 29 insertions(+), 25 deletions(-)

diff --git a/src/mtrr.c b/src/mtrr.c
index 7d1df09..ed239c8 100644
--- a/src/mtrr.c
+++ b/src/mtrr.c
@@ -44,42 +44,42 @@ void mtrr_setup(void)
 
     dprintf(3, "init mtrr\n");
 
-    int i, vcnt, fix, wc;
-    u32 mtrr_cap;
-    union {
-        u8 valb[8];
-        u64 val;
-    } u;
-
-    mtrr_cap = rdmsr(MSR_MTRRcap);
-    vcnt = mtrr_cap & 0xff;
-    fix = mtrr_cap & 0x100;
-    wc = mtrr_cap & 0x400;
+    u32 mtrr_cap = rdmsr(MSR_MTRRcap);
+    int vcnt = mtrr_cap & 0xff;
+    int fix = mtrr_cap & 0x100;
     if (!vcnt || !fix)
        return;
 
-    // Fixed MTRRs
+    // Disable MTRRs
+    wrmsr_smp(MSR_MTRRdefType, 0);
+
+    // Set fixed MTRRs
+    union u64b {
+        u8 valb[8];
+        u64 val;
+    } u;
     u.val = 0;
-    for (i = 0; i < 8; ++i)
+    int i;
+    for (i = 0; i < 8; i++)
         if (RamSize >= 65536 * (i + 1))
             u.valb[i] = MTRR_MEMTYPE_WB;
     wrmsr_smp(MSR_MTRRfix64K_00000, u.val);
     u.val = 0;
-    for (i = 0; i < 8; ++i)
-        if (RamSize >= 65536 * 8 + 16384 * (i + 1))
+    for (i = 0; i < 8; i++)
+        if (RamSize >= 0x80000 + 16384 * (i + 1))
             u.valb[i] = MTRR_MEMTYPE_WB;
     wrmsr_smp(MSR_MTRRfix16K_80000, u.val);
-    wrmsr_smp(MSR_MTRRfix16K_A0000, 0);
-    wrmsr_smp(MSR_MTRRfix4K_C0000, 0);
-    wrmsr_smp(MSR_MTRRfix4K_C8000, 0);
-    wrmsr_smp(MSR_MTRRfix4K_D0000, 0);
-    wrmsr_smp(MSR_MTRRfix4K_D8000, 0);
-    wrmsr_smp(MSR_MTRRfix4K_E0000, 0);
-    wrmsr_smp(MSR_MTRRfix4K_E8000, 0);
-    wrmsr_smp(MSR_MTRRfix4K_F0000, 0);
-    wrmsr_smp(MSR_MTRRfix4K_F8000, 0);
+    wrmsr_smp(MSR_MTRRfix16K_A0000, 0);   // 0xA0000-0xC0000 is uncached
+    int j;
+    for (j = 0; j < 8; j++) {
+        u.val = 0;
+        for (i = 0; i < 8; i++)
+            if (RamSize >= 0xC0000 + j * 0x8000 + 4096 * (i + 1))
+                u.valb[i] = MTRR_MEMTYPE_WP;
+        wrmsr_smp(MSR_MTRRfix4K_C0000 + j, u.val);
+    }
 
-    // Variable MTRRs
+    // Set variable MTRRs
     int phys_bits = 36;
     cpuid(0x80000000u, &eax, &ebx, &ecx, &edx);
     if (eax >= 0x80000008) {
@@ -88,6 +88,10 @@ void mtrr_setup(void)
             phys_bits = eax & 0xff;
     }
     u64 phys_mask = ((1ull << phys_bits) - 1);
+    for (i=0; i<vcnt; i++) {
+        wrmsr_smp(MTRRphysBase_MSR(i), 0);
+        wrmsr_smp(MTRRphysMask_MSR(i), 0);
+    }
     /* Mark 3.5-4GB as UC, anything not specified defaults to WB */
     wrmsr_smp(MTRRphysBase_MSR(0), BUILD_MAX_HIGHMEM | MTRR_MEMTYPE_UC);
     wrmsr_smp(MTRRphysMask_MSR(0)
-- 
2.25.1