From 8e79fc3fa892f3a44f127239012dd3794cc71bbd Mon Sep 17 00:00:00 2001 From: Li-Ta Lo Date: Thu, 15 Apr 2004 17:33:21 +0000 Subject: [PATCH] code reformat git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1505 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/arch/i386/boot/pirq_routing.c | 20 +-- src/arch/i386/boot/tables.c | 1 + src/arch/i386/smp/mpspec.c | 4 +- src/mainboard/tyan/s2885/Config.lb | 6 +- src/mainboard/tyan/s2885/auto.c | 2 +- src/mainboard/tyan/s2885/irq_tables.c | 22 +-- src/mainboard/tyan/s2885/mptable.c | 182 +++++++++++----------- src/northbridge/amd/amdk8/coherent_ht.c | 13 +- src/northbridge/amd/amdk8/incoherent_ht.c | 3 +- 9 files changed, 125 insertions(+), 128 deletions(-) diff --git a/src/arch/i386/boot/pirq_routing.c b/src/arch/i386/boot/pirq_routing.c index bb0f66b28..52e76a77e 100644 --- a/src/arch/i386/boot/pirq_routing.c +++ b/src/arch/i386/boot/pirq_routing.c @@ -15,9 +15,9 @@ void check_pirq_routing_table(void) #if defined(IRQ_SLOT_COUNT) if (sizeof(intel_irq_routing_table) != intel_irq_routing_table.size) { printk_warning("Inconsistent IRQ routing table size (0x%x/0x%x)\n", - sizeof(intel_irq_routing_table), - intel_irq_routing_table.size - ); + sizeof(intel_irq_routing_table), + intel_irq_routing_table.size + ); intel_irq_routing_table.size=sizeof(intel_irq_routing_table); } #endif @@ -30,23 +30,23 @@ void check_pirq_routing_table(void) sum += addr[i]; printk_debug("%s:%6d:%s() - irq_routing_table located at: 0x%p\n", - __FILE__, __LINE__, __FUNCTION__, addr); + __FILE__, __LINE__, __FUNCTION__, addr); sum = rt->checksum - sum; if (sum != rt->checksum) { printk_warning("%s:%6d:%s() - " - "checksum is: 0x%02x but should be: 0x%02x\n", - __FILE__, __LINE__, __FUNCTION__, rt->checksum, sum); + "checksum is: 0x%02x but should be: 0x%02x\n", + __FILE__, __LINE__, __FUNCTION__, rt->checksum, sum); rt->checksum = sum; } if (rt->signature != PIRQ_SIGNATURE || rt->version != PIRQ_VERSION || rt->size % 16 || rt->size < sizeof(struct irq_routing_table)) { printk_warning("%s:%6d:%s() - " - "Interrupt Routing Table not valid\n", - __FILE__, __LINE__, __FUNCTION__); + "Interrupt Routing Table not valid\n", + __FILE__, __LINE__, __FUNCTION__); return; } @@ -56,8 +56,8 @@ void check_pirq_routing_table(void) if (sum) { printk_warning("%s:%6d:%s() - " - "checksum error in irq routing table\n", - __FILE__, __LINE__, __FUNCTION__); + "checksum error in irq routing table\n", + __FILE__, __LINE__, __FUNCTION__); } printk_info("done.\n"); diff --git a/src/arch/i386/boot/tables.c b/src/arch/i386/boot/tables.c index 827b46ed3..b7e4024f5 100644 --- a/src/arch/i386/boot/tables.c +++ b/src/arch/i386/boot/tables.c @@ -47,6 +47,7 @@ struct lb_memory *write_tables(struct mem_range *mem, unsigned long *processor_m post_code(0x9a); check_pirq_routing_table(); + /* This table must be betweeen 0xf0000 & 0x100000 */ rom_table_end = copy_pirq_routing_table(rom_table_end); rom_table_end = (rom_table_end + 1023) & ~1023; diff --git a/src/arch/i386/smp/mpspec.c b/src/arch/i386/smp/mpspec.c index d7b8c3e2f..4a1e233be 100644 --- a/src/arch/i386/smp/mpspec.c +++ b/src/arch/i386/smp/mpspec.c @@ -136,8 +136,8 @@ void smp_write_bus(struct mp_config_table *mc, } void smp_write_ioapic(struct mp_config_table *mc, - unsigned char id, unsigned char ver, - unsigned long apicaddr) + unsigned char id, unsigned char ver, + unsigned long apicaddr) { struct mpc_config_ioapic *mpc; mpc = smp_next_mpc_entry(mc); diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb index b787b1b96..60f4591cc 100644 --- a/src/mainboard/tyan/s2885/Config.lb +++ b/src/mainboard/tyan/s2885/Config.lb @@ -158,7 +158,7 @@ northbridge amd/amdk8 "mc0" pci 0:18.2 pci 0:18.3 southbridge amd/amd8131 "amd8131" link 2 - pci 0:0.0 + pci 0:0.0 pci 0:0.1 pci 0:1.0 pci 0:1.1 @@ -221,8 +221,8 @@ dir /pc80 #dir /bioscall cpu k8 "cpu0" - register "up" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}" - register "down" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}" + register "up" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}" + register "down" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}" end cpu k8 "cpu1" diff --git a/src/mainboard/tyan/s2885/auto.c b/src/mainboard/tyan/s2885/auto.c index 2a620deec..2915886cc 100644 --- a/src/mainboard/tyan/s2885/auto.c +++ b/src/mainboard/tyan/s2885/auto.c @@ -150,6 +150,7 @@ static void main(void) static const struct ht_chain ht_c[] = { { .udev = PCI_DEV(0, 0x18, 0), + /* LDT2 */ .upos = 0xc0, .devreg = 0xe0, }, @@ -179,7 +180,6 @@ static void main(void) setup_s2885_resource_map(); needs_reset = setup_coherent_ht_domain(); -// needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0); needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0])); if (needs_reset) { print_info("ht reset -\r\n"); diff --git a/src/mainboard/tyan/s2885/irq_tables.c b/src/mainboard/tyan/s2885/irq_tables.c index b6a1c1946..cc04c5871 100644 --- a/src/mainboard/tyan/s2885/irq_tables.c +++ b/src/mainboard/tyan/s2885/irq_tables.c @@ -20,16 +20,16 @@ const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x35, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - {3,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0}, - {0x6,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0}, - {0x1,0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0x0, 0}, - {0x5,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0}, - {0x5,(6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0}, - {0x4,(8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0}, - {0x4,(7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0}, - {0x6,(0x0a<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0}, - {0x4,(9<<3)|0, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0}, - {0x6,(0x0b<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, - {0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, + {0x03,(0x4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0}, + {0x06, 0|0, {{0x0, 0x0000}, {0x0, 0x0000}, {0x0, 0x0000}, {0x4, 0xdef8}}, 0, 0}, + {0x01, 0|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0x0, 0}, + {0x05,(0x3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0}, + {0x05,(0x6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0}, + {0x04,(0x8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0}, + {0x04,(0x7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0}, + {0x06,(0xa<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0}, + {0x04,(0x9<<3)|0, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0}, + {0x06,(0xb<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, + {0x06,(0xc<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, } }; diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c index dd7cefcc8..a3afe539f 100644 --- a/src/mainboard/tyan/s2885/mptable.c +++ b/src/mainboard/tyan/s2885/mptable.c @@ -6,19 +6,19 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) { - static const char sig[4] = "PCMP"; + static const char sig[4] = "PCMP"; static const char oem[8] = "TYAN "; static const char productid[12] = "S2885 "; struct mp_config_table *mc; unsigned char bus_num; unsigned char bus_isa; + unsigned char bus_8111_0; + unsigned char bus_8111_1; unsigned char bus_8131_1; unsigned char bus_8131_2; - unsigned char bus_8111_1; unsigned char bus_8151_1; - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -38,81 +38,70 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) smp_write_processors(mc, processor_map); - { + { device_t dev; /* 8111 */ dev = dev_find_slot(3, PCI_DEVFN(0x03,0)); if (dev) { + bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS); bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; printk_debug("bus_isa=%d\n",bus_isa); - } - else { + } else { printk_debug("ERROR - could not find PCI 3:03.0, using defaults\n"); - bus_8111_1 = 6; bus_isa = 7; } + /* 8131-1 */ dev = dev_find_slot(3, PCI_DEVFN(0x01,0)); if (dev) { bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { + } else { printk_debug("ERROR - could not find PCI 3:01.0, using defaults\n"); - bus_8131_1 = 4; } /* 8131-2 */ dev = dev_find_slot(3, PCI_DEVFN(0x02,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { + } else { printk_debug("ERROR - could not find PCI 3:02.0, using defaults\n"); - bus_8131_2 = 5; } - /* 8151 */ + /* 8151 */ dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); if (dev) { bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - printk_debug("bus_8151_1=%d\n",bus_8151_1); - - } - else { + printk_debug("bus_8151_1=%d\n",bus_8151_1); + } else { printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n"); - bus_8151_1 = 2; - } - - + } } - - -/*Bus: Bus ID Type*/ - /* define bus and isa numbers */ - for(bus_num = 0; bus_num < bus_isa; bus_num++) { + /*Bus: Bus ID Type*/ + /* define bus and isa numbers */ + for (bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); } smp_write_bus(mc, bus_isa, "ISA "); -/*I/O APICs: APIC ID Version State Address*/ + /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 2, 0x11, 0xfec00000); { struct pci_dev *dev; uint32_t base; + /* 8131-1 APIC */ dev = dev_find_slot(3, PCI_DEVFN(0x1,1)); if (dev) { base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); base &= PCI_BASE_ADDRESS_MEM_MASK; smp_write_ioapic(mc, 3, 0x11, base); } + /* 8131-2 APIC */ dev = dev_find_slot(3, PCI_DEVFN(0x2,1)); if (dev) { base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -121,77 +110,82 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) } } -/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# -*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, 0x2, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, 0x2, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, 0x2, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x5, 0x2, 0x5); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, 0x2, 0x6); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, 0x2, 0x7); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, 0x2, 0x8); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, 0x2, 0xc); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, 0x2, 0xd); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x2, 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x2, 0xf); -//??? What - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (4<<2)|3, 0x2, 0x13); -//Onboard AMD AC97 Audio ??? - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (4<<2)|1, 0x2, 0x11); -// Onboard AMD USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, 0x2, 0x13); - -// AGP Display Adapter - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, 0x2, 0x10); - -// Onboard Serial ATA - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, 0x2, 0x11); -//Onboard Firewire - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, 0x2, 0x13); -//Onboard Broadcom NIC - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, 0x3, 0x0); - -//Slot 5 PCI 32 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|1, 0x2, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|2, 0x2, 0x12); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|3, 0x2, 0x13); // - -//Slot 3 PCIX 100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|0, 0x3, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|1, 0x3, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, 0x3, 0x1);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, 0x3, 0x2);// - -//Slot 4 PCIX 100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|0, 0x3, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|1, 0x3, 0x3);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|2, 0x3, 0x0);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|3, 0x3, 0x1);// - -//Slot 1 PCI-X 133/100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, 0x4, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, 0x4, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, 0x4, 0x2); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, 0x4, 0x3); // - -//Slot 2 PCI-X 133/100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|0, 0x4, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|1, 0x4, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|2, 0x4, 0x3);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|3, 0x4, 0x0);// - -/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + /* ISA Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, 0x2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, 0x2, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, 0x2, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x5, 0x2, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, 0x2, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, 0x2, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, 0x2, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, 0x2, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, 0x2, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x2, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x2, 0xf); + + /* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */ + // Integrated SMBus 2.0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, (0x04<<2)|3, 0x2, 0x13); + // Integrated AMD AC97 Audio + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, (0x04<<2)|1, 0x2, 0x11); + + // Integrated AMD USB + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x00<<2)|3, 0x2, 0x13); + + // Onboard Serial ATA + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, 0x2, 0x11); + // Onboard Firewire + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, 0x2, 0x13); + + // Onboard Broadcom NIC + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x09<<2)|0, 0x3, 0x0); + + // AGP Display Adapter + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, 0x2, 0x10); + + //Slot 5 PCI 32 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|1, 0x2, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|2, 0x2, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|3, 0x2, 0x13); + + //Slot 3 PCIX 100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|0, 0x3, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|1, 0x3, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|2, 0x3, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|3, 0x3, 0x2); + + //Slot 4 PCIX 100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|0, 0x3, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|1, 0x3, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|2, 0x3, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|3, 0x3, 0x1); + + //Slot 1 PCI-X 133/100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|0, 0x4, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|1, 0x4, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|2, 0x4, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|3, 0x4, 0x3); + + //Slot 2 PCI-X 133/100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|0, 0x4, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|1, 0x4, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|2, 0x4, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|3, 0x4, 0x0); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk_debug("Wrote the mp table end at: %p - %p\n", - mc, smp_next_mpe_entry(mc)); + mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); } diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index baff9deb1..43054ed6e 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -385,10 +385,10 @@ static struct setup_smp_result setup_smp(void) clear_temp_row(0); /* delete temporary connection */ - result.needs_reset = optimize_connection( - NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)), - NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) ); - + result.needs_reset = + optimize_connection(NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)), + NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) ); + #if CONFIG_MAX_CPUS > 2 result.cpus=4; @@ -451,7 +451,8 @@ static struct setup_smp_result setup_smp(void) NODE_HT(2), 0x80 + link_to_register(link_connection(2,3)), NODE_HT(3), 0x80 + link_to_register(link_connection(3,2)) ); -#endif +#endif /* CONFIG_MAX_CPUS > 2 */ + print_debug_hex8(result.cpus); print_debug(" nodes initialized.\r\n"); return result; @@ -644,8 +645,10 @@ static int setup_coherent_ht_domain(void) result = setup_smp(); result.cpus = verify_mp_capabilities(result.cpus); #endif + coherent_ht_finalize(result.cpus); result.needs_reset = apply_cpu_errata_fixes(result.cpus, result.needs_reset); + #if CONFIG_MAX_CPUS > 1 /* Why doesn't this work on the solo? */ result.needs_reset = optimize_link_read_pointers(result.cpus, result.needs_reset); #endif diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index db44650a1..c8eb3c36a 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -316,8 +316,7 @@ static int ht_setup_chains(const struct ht_chain *ht_c, int ht_c_num) reset_needed = 0; next_unitid = 1; - - for(i=0;i